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參數資料
| 型號： | W81C280 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | USB Keyboard/ Device Controller(具有通用串行總線接口的鍵盤／設備控制器) |
| 中文描述： | 8-BIT, MROM, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數： | 12/27頁 |
| 文件大?。?/td> | 328K |
| 代理商： | W81C280 |
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W81C280
Publication Release Date: July 1997
- 8 -
Revision 0.50
6. FUNCTIONAL DESCRIPTION
6.1 First In First Out Storage (FIFO'S) Organization
The W81C280 has six FIFO's, one for receiving and five for transmitting.
FIFO or
SRAM
SIZE (Byte )
NOTES
Endpt 0
Receiving
16
Data received on upstream port which contains the correct address
and pids will be stored here for the CPU core to read.
Endpt 0
Transmitting
16
The CPU core writes the data here which will be sent to the host when
the correct address and pids are transmitted by the host.
Endpt 1
Transmitting
16
The CPU core writes the data here which will be sent to the host when
the correct address and pids are transmitted by the host.
Endpt 2
Transmitting
16
The CPU core writes the data here which will be sent to the host when
the correct address and pids are transmitted by the host.
Endpt 3
Transmitting
16
The CPU core writes the data here which will be sent to the host when
the correct address and pids are transmitted by the host.
Endpt 4
Transmitting
16
The CPU core writes the data here which will be sent to the host when
the correct address and pids are transmitted by the host.
6.1.1 INTERFACE TO THE MICROCONTROLLER:
The FIFOs communicate with the CPU core via a 2-wire serial bus. One signal is the data (P30/MDA)
and the other is the clock (P31/MCL). The clock is always generated by the CPU core. The data is bi-
directional. After each byte of data (MSB first) an acknowledge bit (MDA=0) is sent by the receiver.
The CPU core always initiates the communication with a start condition (MDA from 1 change to 0
while MCL=1) and the FIFO's address. The CPU core ends the transmission with a stop condition
(MDA from 0 change to 1 while MCL=1). Data is always changed while MCL=0 and clocked in on the
rising edge of MCL. The FIFO acts as a slave memory device at address E8h.
the serial BUS
S
ADDRESS
READ FROM FIFO
WRITE TO FIFO
1110 100S
S=1
S=0
相關PDF資料 |
PDF描述 |
|---|---|
| W81E381 | FULL SPEED USB INTEGRATED MICROCONTROLLER |
| W81E381AD | FULL SPEED USB INTEGRATED MICROCONTROLLER |
| W81E381D | FULL SPEED USB INTEGRATED MICROCONTROLLER |
| W82C610 | Monitor Software OSD(On Screen Display) IC(監控軟件屏幕顯示控制器) |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W81E381 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:FULL SPEED USB INTEGRATED MICROCONTROLLER |
| W81E381AD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:FULL SPEED USB INTEGRATED MICROCONTROLLER |
| W81E381D | 制造商:WINBOND 制造商全稱:Winbond 功能描述:FULL SPEED USB INTEGRATED MICROCONTROLLER |
| W-82 | 制造商:Hozan Tool Industrial Co Ltd 功能描述: 制造商:Curtis Industries 功能描述:DIN RAIL SLOTTED |
| W820 | 制造商:LUMINIS 制造商全稱:LUMINIS 功能描述:Post top mount |
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