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參數資料
| 型號： | W81C280 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | USB Keyboard/ Device Controller(具有通用串行總線接口的鍵盤／設備控制器) |
| 中文描述： | 8-BIT, MROM, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數： | 18/27頁 |
| 文件大小： | 328K |
| 代理商： | W81C280 |
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W81C280
Publication Release Date: July 1997
- 14 -
Revision 0.50
6.4 Writing Data To The USB FIFOs and Registers
There are 6 separate memory locations which the CPU core can write to: W81C280 Control
Registers, USB endpoint 0-4 FIFOs. To access the desired memory location, the CPU core follows
the address byte with a memory select byte:
Write to USB endpoint 0:
01h, 61h
Write to USB endpoint 1:
02h, 22h
Write to USB endpoint 2:
06h, 26h
Write to USB endpoint 3:
0ah, 2ah
Write to USB endpoint 4:
0eh, 2eh
Write to Control Registers:
X0h (X = 1~D)
6.4.1 Writing To The Control Registers
The W81C280 contains 7 write-only Control Registers.
ST
1110 1000 AW xxx1 0000 AW
CR0 (8)
AW
CR1 (8)
AW
CR2 (8)
AW
CR3 (8)
AW
CR4(8)
AW
CR5(8)
AW
CR6(8)
AW
SP
CR0 (8) = Control Register 0 (8 bits) (MSB 1st) 11101000= the serial bus's Write Address
xxx : index of control register can be from 000 to 110
The writing to the Control Registers can be started any Control Register dependent on B[7:5] of
sencond byte and discontinued with a 'Stop' after any byte.
6.4.2 Writing To The USB Endpoint 0
Endpoint 0 is used for USB Control transfer for the device. The FIFO is set for a maximum data
packet size of 8 bytes. That is, it can store 8 bytes of data plus sync, PID, and the 2 CRC bytes (12
bytes). The data written to this FIFO will be sent to the host via the USB bus (DP,DM) after the writing
is completed and when any of the following conditions occur:
A token packet is received from the PC with the correct address/endpoint, and an IN PID.
A token packet is received from the PC with the correct address/endpoint, and an OUT or SETUP
PID, followed by data sent from the PC.
If no data is present in the FIFO, a NAK PID will be sent to the host when one of the above conditions
occur. Except after a SETUP PID when an ACK PID will be sent by the W81C180 if no data is
present.
The data sent to the W81C280 FIFO must contain all of the data required to send including the sync,
PID, and CRC's (unless it is chosen that the W81C280 generates the CRC's by H/w generator.) The
CRC's can be generated by the W81C280 by including the number of data bytes to be sent in the
high nibble of the memory select byte.The data sent also requires one stop byte of FFh. The
W81C280 will convert the data to the USB protocol of NRZI, bit stuffing, and LSB first. Once the data
is sent, the FIFO is emptied until new data is written to it.
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