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參數資料
| 型號： | W81E381 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | FULL SPEED USB INTEGRATED MICROCONTROLLER |
| 中文描述： | 全速USB集成微控制器 |
| 文件頁數： | 27/63頁 |
| 文件大小： | 695K |
| 代理商： | W81E381 |
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W81E381D/W81E381AD
Publication Release Date: January 2002
- 27 - Revision 0.52
4.5.9
Register Descriptions - USB Function SFRs (E4)
RXCON
Address: S:E4H
Reset State: 0XX0 0XXXH
Receive FIFO Control Register(Endpoint-Indexed). Controls the receive FIFO specified by EPINDEX.
7
6
5
4
3
2
1
0
RXCLR
-
-
RXFFRC
RXISO
-
-
-
Bit
Number
7
Bit
Mnemonic
RXCLR
Function
Receive FIFO Clear:
Set this bit to flush the entire receive FIFO. All flags in RXFLG revert to
their reset states (RXEMP is set; the other flags cleard) and all the
read/write pointers and markers are read. The RXISO bit in this register
and the RXSEQ bit in the RXSTAT register are not affected by this
operation. Hardware clears this bit when the flush operation is
completed.
Reserved:
The value read from this bit is indeterminate. Write zero to this bit.
Reserved:
The value read from this bit is indeterminate. Write zero to this bit.
FIFO Read Complete:
Set this bit to release the receive FIFO when data set read is complete.
Setting this bit "clears" the RXFIF "bit" in the RXFLG register
corresponding to the data set that was just read. Hardware clears this bit
after the RXFIF bit is cleared. All data from this data set must have been
read.
Note: that RXFFRC only works if STOVW and EDOVW are cleared.
Receive Isochronous Data:
Set this bit to indicate that the receive FIFO is programmed to receive
isochronous data and to set up the USB interface to handle an
isochronous data transfer. This bit is not reset when the RXCLR bit is
set; it must be cleared by firmware.
Reserved:
The value read from this bit is indeterminate. Write zero to this bit.
Reserved:
The value read from this bit is indeterminate. Write zero to this bit.
Reserved:
The value read from this bit is indeterminate. Write zero to this bit.
6
-
5
-
4
RXFFRC
3
RXISO
2
-
1
-
0
-
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相關代理商/技術參數 |
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