
W81E381D/W81E381AD
Publication Release Date: January 2002
- 31 - Revision 0.52
continued
Bit
Number
Bit
Mnemonic
Function
2
RXFULL
Receive FIFO Full Flag (read-only):
Hardware sets this flag when the write pointer has rolled over and equals
the read pointer. Hardware clears the bit when the full condition no longer
exists. This is not a sticky bit and always tracks the current status of the
receive FIFO, regardless of ISO or non-ISO mode.
1
RXURF
Receive FIFO Under-run Flag:
Hardware sets this bit when an additional byte is read from an empty
receive FIFO or RXCNT. Hardware does not clear this bit, so you must
clear it in firmware. When the receive FIFO under-run, the read point will bit
advance-it remains locked in the empty position.
Note: that you must check the RXURF flag after reads from the receive
FIFO before setting the RXFFRC bit in RXCON. When the bit is set, the
FIFO is in an unknown state and all transmissions are “NAK”ed. It is
recommended that you reset the FIFO in the error management routine
using the RXCLR bit in the RXCON register.
0
RXOVF
Receive FIFO Overrun Flag:
Hardware sets this bit when FIU/HIU writes an additional byte to a full
receive FIFO or writes a byte count to RXCNT with RXFIFO=1.This is a
sticky bit that must be cleared through firmware, although it can be cleared
by hardware if a SETUP packet is received after RXOVF error had already
occurred. When the receive FIFO overruns, the write pointer will not
advance- it remains locked in the full position.
Note: that when the bit is set, the FIFO is in an unknown state and all
transmissions are “NAK”ed. It is recommended that you reset the FIFO in
the error management routine using the RXCLR bit in the RXCON register.