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參數資料
| 型號： | W83194BR-39B |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | XO, clock |
| 英文描述： | STEP-LESS 3-DIMM CLOCK |
| 中文描述： | 155 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數： | 13/20頁 |
| 文件大小： | 276K |
| 代理商： | W83194BR-39B |
W83194BR-39B
PRELIMINARY
Publication Release Date: June 2000
- 13 - Revision 0.46
8.0 SPECIFICATIONS
8.1 ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device.
Precautions should be taken to avoid application of any voltage higher than the maximum rated
voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability.
Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd).
Symbol
Parameter
Voltage on any pin with respect to GND
Rating
Vdd , V
IN
- 0.5 V to + 7.0 V
T
STG
Storage Temperature
- 65
°
C to + 150
°
C
T
B
Ambient Temperature
- 55
°
C to + 125
°
C
T
A
Operating Temperature
0
°
C to + 70
°
C
8.2 AC CHARACTERISTICS
Vdd = Vddq3 = 3.3V 5 %, Vddq2 = VddL1=VddL2 = 2.375V~2.9V , T
A
= 0 C to +70 C
Parameter
Symbol
Min
Output Duty Cycle
45
CPU/SDRAM to PCI Offset
t
OFF
1
Skew (CPU-CPU), (PCI-
PCI), (SDRAM-SDRAM)
CPU/SDRAM
Cycle to Cycle Jitter
CPU/SDRAM
Absolute Jitter
Jitter Spectrum 20 dB
Bandwidth from Center
Output Rise (0.4V ~ 2.0V)
& Fall (2.0V ~0.4V) Time
t
THL
Overshoot/Undershoot
Beyond Power Rails
Ring Back Exclusion
V
RBE
0.7
Typ
50
2.6
Max
55
4
Units
%
ns
Test Conditions
Measured at 1.5V
15 pF Load Measured at 1.5V
t
SKEW
250
ps
15 pF Load Measured at 1.5V
t
CCJ
±250
ps
t
JA
500
ps
BW
J
500
KHz
t
TLH
0.4
1.6
ns
15 pF Load on CPU and PCI
outputs
V
over
0.7
1.5
V
22
at source of 8 inch PCB
run to 15 pF load
2.1
V
Ring Back must not enter this
range.
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