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參數資料
| 型號： | W83194BR-39B |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | XO, clock |
| 英文描述： | STEP-LESS 3-DIMM CLOCK |
| 中文描述： | 155 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數： | 4/20頁 |
| 文件大小： | 276K |
| 代理商： | W83194BR-39B |
W83194BR-39B
PRELIMINARY
Publication Release Date: June 2000
- 4 - Revision 0.46
4.3 I
2
C Control Interface
SYMBOL
PIN
I/O
FUNCTION
SDATA*
23
I/O
Serial data of I
2
C 2-wire control interface
Serial clock of I
2
C 2-wire control interface
SDCLK*
24
IN
4.4 Fixed Frequency Outputs
SYMBOL
PIN
2
I/O
I/O
FUNCTION
REF0^ / PD#
14.318MHz reference clock. This REF output is the
stronger buffer for ISA bus loads.(pin7 *Mode0=1)
Halt all clocks at logic 0 level, when input low (pin7
*Mode0=0)
14.318MHz reference clock.
Latched input for FS2 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
24MHz output clock.
Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
48MHz output for USB during normal operation.
Latched input for FS0 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
REF1 / FS2*
46
I/O
24MHz / FS1*
25
I/O
48MHz / FS0*
26
I/O
4.5 Power Pins
SYMBOL
PIN
1
48
42
6, 14
19, 30, 36
FUNCTION
Vddq1
VddL1
VddL2
Vddq2
Vddq3
Power supply for Ref [0:1] crystal and core logic.
Power supply for IOAPIC output, either 2.5V or 3.3V.
Power supply for CPUCLK[0:3], either 2.5V or 3.3V.
Power supply for PCICLK_F, PCICLK[0:4], 3.3V.
Power supply for SDRAM[0:12], and CPU PLL core,
nominal 3.3V.
Power for 24 & 48MHz output buffers and fixed PLL
core.
3,9,16,22,33,39,45 Circuit Ground.
Vddq4
27
Vss
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