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參數(shù)資料
| 型號(hào)： | W83194BR-39B |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | XO, clock |
| 英文描述： | STEP-LESS 3-DIMM CLOCK |
| 中文描述： | 155 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁(yè)數(shù)： | 17/20頁(yè) |
| 文件大小： | 276K |
| 代理商： | W83194BR-39B |
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W83194BR-39B
PRELIMINARY
Publication Release Date: June 2000
- 17 - Revision 0.46
9.0 OPERATION OF DUAL FUCTION PINS
Pins 2, 7, 8, 25, and 26 are dual function pins and are used for selecting different functions in this
device (see Pin description). During power up, these pins are in input mode (see Fig1), therefore,
and are considered input select pins. When Vdd reaches 2.5V, the logic level that is present on these
pins is latched into their appropriate internal registers. Once the correct information is properly
latched, these pins will change into output pins and will be pulled low by default. At the end of the
power up timer (within 3 ms) outputs starts to toggle at the specified frequency.
Within 3ms
Input
Output
Output tri-state
Output pull-low
2.5V
Output tri-state
Output pull-low
#7 PCICLK_F/MODE
#46 REF1/FS2
#25 24/FS1
#26 48/FS0
All other clocks
Vdd
Each of these pins has a large pull-up resistor ( 250 k
@3.3V ) inside. The default state will be logic
1, but the internal pull-up resistor may be too large when long traces or heavy load appear on these
dual function pins. Under these conditions, an external 10 k
resistor is recommended to be
connected to Vdd if logic 1 is expected. Otherwise, there should be direct connection to ground if a
logic 0 is desired. The 10 k
resistor should be placed before the serious terminating resistor. Note
that these logic will only be latched at initial power on.
If optional EMI reducing capacitor are needed, they should be placed as close to the series
terminating resistor as possible and after the series terminating resistor. These capacitors have
typical values ranging from 4.7pF to 22pF.
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