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參數(shù)資料
| 型號： | W83194BR-39B |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | XO, clock |
| 英文描述： | STEP-LESS 3-DIMM CLOCK |
| 中文描述： | 155 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大小： | 276K |
| 代理商： | W83194BR-39B |
W83194BR-39B
PRELIMINARY
Publication Release Date: June 2000
- 6 - Revision 0.46
6.0 MODE PIN -POWER MANAGEMENT INPUT CONTROL
MODE0, Pin7 (Latched Input)
PIN 2
0
PD# (Input)
1
REF0 (Output)
7.0 FUNCTION DESCRIPTION
7.1 2-WIRE I
2
C CONTROL INTERFACE
The clock generator is a slave I
2
C component which can be read back the data stored in the latches
for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire
control interface allows each clock output individually enabled or disabled. On power up, the
W83194BR-39Binitializes with default register settings. Use of the 2-wire control interface is then
optional.
The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high
during normal data transfer. There are only two exceptions. One is a high-to-low transition on
SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a
low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated.
Byte writing starts with a “start” condition followed by 7-bit slave address and a write command bit
[1101 0010], command code checking [0000 0000], and byte count checking. After successful
reception of each byte, an “acknowledge“ (low) on the SDATA wire will be generated by the clock
chip. Controller can start to write to internal I
2
C registers after the string of data. The sequence
order is as follows:
Bytes sequence order for I
2
C controller :
Clock Address
A(6:0) & R/W
Ack
8 bits dummy
Command code
Ack
8 bits dummy
Byte count
Ack
Byte0,1,2...
until Stop
Set R/W to 1 when ead back”, the data sequence is as follows :
Clock Address
A(6:0) & R/W
Ack
Byte 0
Ack
Ack
Byte2, 3, 4...
until Stop
Byte 1
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