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參數資料
型號: W83787IF
廠商: WINBOND ELECTRONICS CORP
元件分類: 外設及接口
英文描述: WINBOND I/O WITH SERIAL-INFRARED SUPPORT
中文描述: MULTIFUNCTION PERIPHERAL, PQFP100
封裝: PLASTIC, QFP-100
文件頁數: 55/123頁
文件大小: 1751K
代理商: W83787IF
W83787IF
Publication ReleaseDate:Sep 1995
- 55 -
Revision A1
101
110
Reserved.
Test Mode. The FIFO may be written and read in this mode, but the data will not be
transmitted on the parallel port.
Configuration Mode. The confgA and confgB registers are accessible at 0x400 and
0x401 in this mode.
Bit 4: Read/Write (Valid only in ECP Mode)
1
Disables the interrupt generated on the asserting edge of nFault.
0
Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted
(interrupt) an interrupt will be generated and this bit is written from a 1 to 0.
Bit 3: Read/Write
1
Enables DMA.
0
Disables DMA unconditionally.
Bit 2: Read/Write
1
Disables DMA and all of the service interrupts.
0
Enables one of the following cases of interrupts. When one of the service interrupts
has occurred, the serviceIntr bit is set to a 1 by hardware. This bit must be reset to 0
to re-enable the interrupts. Writing a 1 to this bit will not cause an interrupt.
(a) dmaEn = 1:
During DMA this bit is set to a 1 when terminal count is reached.
(b) dmaEn = 0 direction = 0:
This bit is set to 1 whenever there are writeIntr Threshold or more bytes free in
the FIFO.
(c) dmaEn = 0 direction = 1:
This bit is set to 1 whenever there are readIntr Threshold or more valid bytes to
be read from the FIFO.
Bit 1: Read only
0
The FIFO has at least 1 free byte.
1
The FIFO cannot accept another byte or the FIFO is completely full.
Bit 0: Read only
0
The FIFO contains at least 1 byte of data.
1
The FIFO is completely empty.
111
5.3.11 Bit Map of ECP Port Registers
D7
D6
D5
D4
D3
D2
D1
D0
NOTE
data
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
ecpAFifo
Addr/RLE
Address or RLE field
2
dsr
nBusy
nAck
PError
Select
nFault
1
1
1
1
dcr
1
1
Directio
ackIntEn
SelectIn
nInit
autofd
strobe
1
cFifo
Parallel Port Data FIFO
2
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