
W83877ATF
Publication Release Date: April 1998
- 165 -
Version 0.51
8.4.21 Bit Map Configuration Registers
Table 8-4: Bit Map of PM1 Register Block
Register
Address
Power-On
Reset
Value
D7
D6
D5
D4
D3
D2
D1
D0
PM1STS1
<CR33>
0000 0000
0
0
GBL_STS
BM_STS
0
0
0
TMR_STS
PM1STS2
<CR33>+1H
0000 0000
WAK_STS
0
0
0
0
0
0
0
PM1EN1
<CR33>+2H
0000 0000
0
0
GBL_EN
0
0
0
0
TMR_EN
PM1EN2
<CR33>+3H
0000 0000
0
0
0
0
0
0
0
0
PM1CTL1
<CR33>+4H
0000 0000
0
0
0
0
0
GBL_RLS
BM_RLD
SCI_EN
PM1CTL2
<CR33>+5H
0000 0000
0
0
0
0
0
0
0
0
PM1CTL3
<CR33>+6H
0000 0000
0
0
0
0
0
0
0
0
PM1CTL4
<CR33>+7H
0000 0000
0
0
0
0
0
0
0
0
PM1TMR1
<CR33>+8H
0000 0000
TMR_VAL7
TMR_VAL6
TMR_VAL5
TMR_VAL4
TMR_VAL3
TMR_VAL2
TMR_VAL1
TMR_VAL0
PM1TMR2
<CR33>+9H
0000 0000
TMR_VAL15
TMR_VAL14
TMR_VAL13
TMR_VAL12
TMR_VAL11
TMR_VAL10
TMR_VAL9
TMR_VAL8
PM1TMR3
<CR33>+AH
0000 0000
TMR_VAL23
TMR_VAL22
TMR_VAL21
TMR_VAL20
TMR_VAL19
TMR_VAL18
TMR_VAL17
TMR_VAL16
PM1TMR4
<CR33>+BH
0000 0000
0
0
0
0
0
0
0
Table 8-5: Bit Map of GPE Register Block
Register
Address
Power-On
Reset Value
D7
D6
D5
D4
D3
D2
D1
D0
GP0STS1
<CR34>
0000 0000
0
0
0
0
PRTSCISTS
FDCSCISTS
URASCISTS
URBSCISTS
GP0STS2
<CR34>+1H
0000 0000
0
0
0
0
0
0
0
0
GP0EN1
<CR34>+2H
0000 0000
0
0
0
0
PRTSCIEN
FDCSCIEN
URASCIEN
URBSCIEN
GP0EN2
<CR34>+3H
0000 0000
0
0
0
0
0
0
0
0
GP1STS1
<CR34>+4H
0000 0000
0
0
0
0
0
0
0
BIOS_STS
GP1STS2
<CR34>+5H
0000 0000
0
0
0
0
0
0
0
0
GP1EN1
<CR34>+6H
0000 0000
0
0
0
0
0
0
TMR_ON
BIOS_EN
GP1EN2
<CR34>+7H
0000 0000
0
0
0
0
0
0
BM_CNTRL
BIOS_RLS