
W83877ATF
Publication Release Date: April 1998
- 35 -
Version 0.51
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC and reduced write current control.
00 500 KB/S (MFM), 250 KB/S (FM), RWC = 1.
01 300 KB/S (MFM), 150 KB/S (FM), RWC = 0.
10 250 KB/S (MFM), 125 KB/S (FM), RWC = 0.
11 1 MB/S (MFM), Illegal (FM), RWC = 1.
The 2MB/S data rate for Tape drive is only supported by setting 01 to DRATE1 and DRATE0 bits, as
well as setting 10 to DRTA1 and DRTA0 bits
,
which are two of the Configuration CR2D. Please refer
to the function of CR2D and the data rate table for individual data rates setting.
2.2.7 FIFO Register (R/W base address + 5)
The Data Register consists of four status registers in a stack
,
with only one register presented to the
data bus at a time. This register stores data, commands, and parameters
,
and provides diskette-drive
status information. Data bytes are passed through the data register to program or obtain results after
a command. In the W83877ATF, this register defaults to FIFO disabled mode after reset. The FIFO
can change its value and enable its operation through the CONFIGURE command.
Status Register 0 (ST0)
7-6
5
4
3
2
1-0
US1, US0 Drive Select:
00 Drive A selected
01 Drive B selected
10 Drive C selected
11 Drive D selected
HD Head address:
1 Head selected
0 Head selected
NR Not Ready:
1 Drive is not ready
0 Drive is ready
EC Equipment Check:
1 When a fault signal is received from the FDD or the track
0 signal fails to occur after 77 step pulses
0 No error
SE Seek end:
1 seek end
0 seek error
IC Interrupt Code:
00 Normal termination of command
01 Abnormal termination of command
10 Invalid command issue
11 Abnormal termination because the ready signal from FDD changed state during command execution