
Preliminary W91030
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Demodulated
internal
bit stream
start
0
b0
b1
b2
b3
b4
b5
b6
b7
1
0
stop
stop
start
DATA
b0 b1 b2 b3 b4 b5 b6 b7
DCLK
FDRN
1/f
DCLK1
b7
b6
b5
1
b0
b0
b7
b6
t
DDS
t
DDH
Nth byte data
(N + 1)th byte data
(N - 1)th byte data
Nth byte data
t
RL
Note 2
Note 1
1. FDRN cleared to high by DCLK.
2. FDRN not cleared, low for maximum time (1/2 bit width).
Notes:
Figure 7-8. Serial Data Interface Timing of FSK Demodulation in Mode 1
Other Functions
Operation Modes
The two operation modes of the W91030 are known as M-mode and C-Mode and the timing
difference related to these two mode are on the INTN and ALGO/DET pins.
In M-mode (MODE pin high), the ALGO/DET pin is used as a dual tone alert signal guard time detect
output. The microcontroller must monitor the RNGON pin during ring detection, monitor the ALGO pin
during alert tone detection and monitor the FCDN pin during FSK demodulation.
In C-mode (MODE pin low), the ring detect output, alert guard time output and FSK carrier detect
outpout also will be reflected on the ALGO/DET output pin. The microcontroller may monitor the
ALGO/DET pin during ring detection, during alert tone detection and during FSK demodulation. The
interrupt outputs only after the end of the alerting guard time when the dual tone alert signal has been
detected. The microcontroller must enable the FSK demodulation when an interrupt occurs at the end
of the alerting guard time detection.
Interrupt
The interrupt INTN is an open drain output and is used to interrupt the microcontroller. Either RNGON
low, FDRN low or ALGO high (in M-mode) will set INTN low and will remain low until all of these three
pins return to an inactive state. The microcontroller must read these pins to know what kind of
interrupt occurred and to make the correct interrupt response. In C-mode, the interrupt outputs only
after the end of the alerting guard time when the dual tone alert signal has been detected.
When the system is powered on, there is no charge on the capacitors. The voltage on the RNGRC pin
is low and RNGON will be low. Also the voltage on the ALGRC pin is high and ALGO will be high if
the SLEEP pin is low. This will cause an interrupt upon power up which will not be cleared until both