
W9816G6BB
Publication Release Date: January 2, 2003
- 5 -
Revision A1
5. BALL DESCRIPTION
BALL-LOCATION
BALL
NAME
FUNCTION
DESCRIPTION
N6, P7, P6, R6,
R2, P2, P1, N2,
N1, M2, N7
A0
A10
Address
Multiplexed pins for row and column address.
Row address: A0
A10. Column address: A0
A7.
M1
BA
Bank
Address
Select bank to activate during row address latch
time, or bank to read/write during column address
latch time.
A6, B7, C7, D7, D6,
E7, F7, G7, G1, F1,
E1, D2, D1, C1, B1,
A2,
DQ0
DQ15
Data Input/
Output
Multiplexed pins for data input and output.
L7
CS
Chip Select
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
the clock,
RAS
,
CAS
and
WE
define the
operation to be executed.
K6
RAS
Row Address
Strobe
K7
CAS
Column
Address
Strobe
Referred to
RAS
J7
WE
Write Enable Referred to
RAS
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
Power
(+3.3V)
DRAM.
Ground for input buffers and logic circuit inside
DRAM.
Power
(+3.3V) for
I/O buffer
Ground for
I/O buffer
to improve noise immunity.
J2/J6
UDQM/
LDQM
Input/Output
Mask
K2
CLK
Clock Inputs
L1
CKE
Clock Enable
A7, R7
V
DD
Power for input buffers and logic circuit inside
A1, R1
V
SS
Ground
B6, C2, E6, F2
V
DDQ
Separated power from V
DD
, used for output buffers
to improve noise immunity.
B2, C6, E2, F6
V
SSQ
Separated ground from V
SS
, used for output buffers
G2, G6, H1, H2, H6,
H7, J1, K1, L2, L6,
M6, M7
NC
No
Connection
No connection