
W9816G6BB
Publication Release Date: January 2, 2003
- 9 -
Revision A1
the clock. The data DQs go to a high impedance state after a delay, which is equal to the
CAS
Latency in a burst read cycle, interrupted by Burst Stop. If a Burst Stop Command is issued during a
full page burst write operation, then any residual data from the burst write cycle will be ignored.
Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address, which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 2
.
Table 2 Address Sequence of Sequential Mode
Data
Access Address
Burst Length
Data 0
n
BL = 2 (disturb address is A0)
Data 1
n + 1
No address carry from A0 to A1
Data 2
n + 2
BL = 4 (disturb addresses are A0 and A1)
Data 3
n + 3
No address carry from A1 to A2
Data 4
n + 4
Data 5
n + 5
BL = 8 (disturb addresses are A0, A1 and A2)
Data 6
n + 6
No address carry from A2 to A3
Data 7
n + 7
Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit
in the sequence shown in Table 3.
Table 3 Address Sequence of Interleave Mode
Data
Access Address
Bust Length
Data 0
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 2
Data 1
A8 A7 A6 A5 A4 A3 A2 A1
A0
Data 2
A8 A7 A6 A5 A4 A3 A2
A1
A0
BL = 4
Data 3
A8 A7 A6 A5 A4 A3 A2
A1
A0
Data 4
A8 A7 A6 A5 A4 A3
A2
A1 A0
BL = 8
Data 5
A8 A7 A6 A5 A4 A3
A2
A1
A0
Data 6
A8 A7 A6 A5 A4 A3
A2
A1
A0
Data 7
A8 A7 A6 A5 A4 A3
A2
A1
A0