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參數資料
| 型號： | WFP6852A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 顯示驅動器 |
| 英文描述： | 300-Channel, 6-Bit Signal Driver for TFT-LCD Applications(用于TFT型液晶顯示器的300通道的，6點式信號驅動器) |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC340 |
| 封裝： | DIE-340 |
| 文件頁數： | 17/21頁 |
| 文件大小： | 508K |
| 代理商： | WFP6852A |
January 27, 2000
Rev. 0.02
1999 Winbond Electronics Corporation
17
WFP6852A
300-Channel 6-Bit Signal Driver
9.5
AC Characteristics (
V
DDD
= 3.3 V ± 0.3 V
)
–
(Preliminary data – subject to change)
See Figures 9-1 to 9-6 for waveforms.
Conditions: V
DDA
= 5.0 V ± 0.5 V, T
A
= 25° C
Symbol
Parameter
Min
Max
Units
Note
2xCLK/2xCLK
2xCLK/2xCLK
f
CLK
Guaranteed Max DCLK frequency
55/27.5
MHz
t
CLK
DCLK period
18.2/36.4
ns
t
1
DCLK high pulse width
6/12
ns
t
2
DCLK low pulse width
6/12
ns
t
3
DCLK rise time
6/6
ns
t
4
DCLK fall time
6/6
ns
t
5
Data, DATA_INV setup time
2/1
ns
t
6
Data, DATA_INV hold time
10/11
ns
t
7
Enable-In setup time
3/3
ns
t
8
Enable-In hold time
10/ 1/2 DCLK
t
9
DCLK
to Enable-Out
12/12
ns
1
t
10
LP high pulse width
50/50
ns
t
11
LP low pulse width
100/100
ns
2
t
12
Last Pixel DCLK to LP
10/10
ns
t
13
Blanking Time
2/1
DCLK’s
NOTES:
1)
C
LOAD
= 15 pF (See Figure 9-7)
2) Free running DCLK operation: LP must be sampled low by at least 1 rising edge of DCLK
before the DCLK edge which samples LP high. Stopped DCLK operation: LP must be sam-
pled low by one rising edge of DCLK before DCLK is stopped.
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