
8
1999 Winbond Electronics Corporation
January 27, 2000
Rev. 0.02
WFP6852A
300-Channel 6-Bit Signal Driver
Name
Number
Type
Description
(Cont.)
V
S1
-V
S300
O
VOLTAGE OUTPUTS
: These outputs drive all 300 pixel
inputs of the LCD simultaneously after the high-to-low tran-
sition of LP.
D
00
-D
05
D
10
-D
15
D
20
-D
25
28-33
22-27
10-15
I
DATA
: The Data inputs consist of 6-bit words for each of
three channels. D
i5
indicates the MSB and D
i0
the LSB.
All 3 data words are loaded in parallel.
LP
16
I
Latch Pulse
: When LP is driven high, the display data is
transferred from the Input Register into the Storage Register
for all 300 channels. If DCLK is stopped, when LP goes low,
all 300 outputs drive to the selected analog voltages.
If DCLK is free running, the outputs begin to drive on the first
rising edge of DCLK which samples LP high.
DCLK
19
I
DATA CLOCK
: Data is loaded into the input registers on the
‘’low-to-‘high’ transition of DCLK when 2xCLK = logic low.
Data is loaded into the input registers on both edges of
DCLK when 2xCLK = logic high.
V
DDD
18
I
DIGITAL SUPPLY VOLTAGE
: 2.5 V or 3.3 V should be pro-
vided on this pin to supply digital power to the device.
Last
First
First
Last
Data
from channel
V
S1
to V
S300
(LD1_300 = ‘1’)
loaded
Data
from channel
V
S300
to V
S1
(LD1_300 = ‘0’)
loaded
D
25
-D
20
D
15
-D
10
D
05
-D
00
D
25
-D
20
D
15
-D
10
D
05
-D
00
V
S300
V
S299
V
S298
V
S3
V
S2
V
S1
V
S300
V
S299
V
S298
V
S3
V
S2
V
S1
D
25
-D
20
D
15
-D
10
D
05
-D
00
.
D
25
-D
20
D
15
-D
10
D
05
-D
00
D
25
-D
20
D
15
-D
10
D
05
-D
00
.
D
25
-D
20
D
15
-D
10
D
05
-D
00
Figure 7–1. Display Data Sampling and Output Direction