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參數(shù)資料
| 型號(hào)： | WFP6852A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 顯示驅(qū)動(dòng)器 |
| 英文描述： | 300-Channel, 6-Bit Signal Driver for TFT-LCD Applications(用于TFT型液晶顯示器的300通道的，6點(diǎn)式信號(hào)驅(qū)動(dòng)器) |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC340 |
| 封裝： | DIE-340 |
| 文件頁數(shù)： | 9/21頁 |
| 文件大小： | 508K |
| 代理商： | WFP6852A |
January 27, 2000
Rev. 0.02
1999 Winbond Electronics Corporation
9
WFP6852A
300-Channel 6-Bit Signal Driver
Name
Number
Type
Description
(Cont.)
V
DDA
2
I
ANALOG SUPPLY VOLTAGE
: Up to 5.0 V should be pro-
vided on this pin to supply analog power to the device.
Also,
must have V
DDA
>= V
DDD
.
V
10
V
9
V
8
V
7
V
6
V
5
V
4
V
3
V
2
V
1
V
0
3
38
4
37
5
36
6
35
7
34
8
I
REFERENCE ANALOG VOLTAGE INPUTS:
These
11 inputs are used to supply the adjustable-reference volt-
age inputs to the resistor-string DAC to provide the desired
transmissivity-voltage response.
.
AGND
39
I
ANALOG
GROUND
DGND
20
I
DIGITAL GROUND
DATA_INV
40
I
DATA INVERSION
: When logic high, enables inversion of
the input display data (D
ij
). This pad should be tied “l(fā)ow” or
allowed to float if data inversion is not used. This signal may
also be used in coordination with the control ASIC to reduce
data transitions.
This pad has an internal pull-down and
is disabled if no-connect
.
2xCLK
1
I
2xCLK
: When logic high, the 2xCLK input enables sampling
of input display data (D
ij
) on
both
rising and falling edges of
the DCLK input (see Fig. 9-2). When logic low, input data is
sampled on the falling edge of DCLK only (Fig. 9-1).
This
pad has an internal pull-down and is disabled if no-con-
nect
.
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