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參數資料
| 型號： | W29D040C |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 512K×8bit CMOS Flash Memory(512K×8位CMOS閃速存儲器) |
| 中文描述： | 為512k × 8位的CMOS閃存（為512k × 8位的CMOS閃速存儲器） |
| 文件頁數： | 10/40頁 |
| 文件大小： | 280K |
| 代理商： | W29D040C |
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W29D040C
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only operating function of the device under this condition. The
CE
circuit will partially power down the
device under these conditions (to approximately 2 mA). The OE and
WE
pins will control the output
disable functions as described in "Device Bus Operations".
The DQ5 failure condition will also appear if a user tries to program a 1 to a location that is previously
programmed to 0. In this case the device locks out and never completes the Embedded Program
Algorithm. Hence, the system never reads a valid data on DQ7 bit and DQ6 never stops toggling. Once
the device has exceeded timing limits, the DQ5 bit will indicate a "1". Please note that this is not a
device failure condition since the device was incorrectly used. If this occurs, reset the device.
DQ3: Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin.
DQ3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial
sector erase command sequence.
If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, DQ3
may be used to determine if the sector erase timer window is still open. If DQ3 is high ("1") the internally
controlled erase cycle has begun; attempts to write subsequent commands (other than Erase Suspend)
to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle
Bit. If DQ3 is low ("0"), the device will accept additional sector erase commands. To insure the command
has been accepted, the system software should check the status of DQ3 prior to and following each
subsequent sector erase command. If DQ3 were high on the second status check, the command may
not have been accepted.
Refer to "Hardware Sequence Flags".
DQ2: Toggle Bit 2
This toggle bit, along with DQ6, can be used to determine whether the device is in the Embedded Erase
Algorithm or in Erase suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase
Algorithm. If the device is in the erase suspend-read mode, successive reads from the erase-suspend
sector will cause DQ2 to toggle. When the device is in the erase suspend-program mode, successive
reads from the byte address of the non-erase suspend sector will indicate a logic "1" at the DQ2 bit.
Note that a sector which is selected for erase is not available for read in Erase Suspend mode. Other
sectors which are not selected for Erase can be read in Erase Suspend.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or erase, or erase
suspend program operation is in progress.
If the DQ5 failure condition is observed while in Sector Erase mode (i.e., exceeded timing limits), the
DQ2 toggle bit can give extra information. In this case, the normal function of DQ2 is modified.
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