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參數資料
| 型號： | W29D040C |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 512K×8bit CMOS Flash Memory(512K×8位CMOS閃速存儲器) |
| 中文描述： | 為512k × 8位的CMOS閃存（為512k × 8位的CMOS閃速存儲器） |
| 文件頁數： | 7/40頁 |
| 文件大小： | 280K |
| 代理商： | W29D040C |
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W29D040C
Publication Release Date: January 1999
- 7 -
Revision A1
or
WE
(whichever happens first) begins programming using the Embedded Program Algorithm. Upon
executing the algorithm, the system is not required to provide further controls or timings. The device will
automatically provide adequate internally generated program pulses and verify the programmed cell
margin.
The automatic programming operation is completed when the data on DQ7 (also used as Data Polling) is
equivalent to the data written to this bit at which time the device returns to the read mode and addresses
are no longer latched (see "Hardware Sequence Flags").Therefore, the device requires that a valid
address to the device be supplied by the system at this particular instance of time for Data Polling
operations. Data Polling must be performed at the memory location which is being programmed.
Any commands written to the chip during the Embedded Program Algorithm will be ignored. If a hardware
reset occurs during the programming operation, the data at that particular location will be corrupted.
Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot
be programmed back to a "1". Attempting to program 0 back to 1, will produce a "1" at the DQ5 output,
the toggle bit will stop toggling. Only erase operations can convert "0"s to "1"s.
Refer to the Embedded Programming Algorithm using typical command strings and bus operations.
Chip Erase Command
Chip erase is a six-bus-cycle operation. There are two "unlock" write cycles. These are followed by
writing the "set-up" command. Two more "unlock" write cycles are then followed by the chip erase
command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded
Erase Algorithm command sequence the device will automatically erase and verify the entire memory for
an all one data pattern. The erase is performed simultaneously on all sectors at the same time (see
"Feature"). The system is not required to provide any controls or timings during these operations.
The automatic erase begins on the rising edge of the last
WE
pulse in the command sequence and
terminates when the data on DQ7 is "1" at which time the device returns to read the mode.
Refer to the Embedded Erase Algorithm using typical command strings and bus operations.
Sector Erase Command
Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by
writing the "set-up" command. Two more "unlock" write cycles are then followed by the sector erase
command. The sector address (any address location within the desired sector) is latched on the falling
edge of
WE
, while the command (30H) is latched on the rising edge of
WE
. After a time-out of 80
μ
S
from the rising edge of the last sector erase command, the sector erase operation will begin.
Multiple sectors may be erased sequentially by writing the six bus cycle operations as described above.
This sequence is followed with writes of the Sector Erase command to addresses in other sectors
desired to be sequentially erased. The time between writes must be less than 80
μ
s otherwise that
command will not be accepted and erasure will start. It is recommended that processor interrupts be
disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last
Sector Erase command is written. A time-out of 80
μ
s from the rising edge of the last
WE
will initiate the
execution of the Sector Erase command(s). If another falling edge of the
WE
occurs within the 80
μ
S
time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still
open. See DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during
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