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參數(shù)資料
型號(hào): W79E201A16PN
廠商: WINBOND ELECTRONICS CORP
元件分類: 微控制器/微處理器
英文描述: 8-BIT MICROCONTROLLER
中文描述: 8-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQCC44
封裝: ROHS COMPLIANT, PLASTIC, LCC-44
文件頁數(shù): 17/87頁
文件大小: 818K
代理商: W79E201A16PN
W79E201
Publication Release Date: December 16, 2004
- 17 -
Revision A2
BIT
NAME
FUNCTION
7~0
SBUF
Serial data on the serial port is read from or written to this location. It actually
consists of two separate internal 8-bit registers. One is the receive resister, and the
other is the transmit buffer. Any read access gets data from the receive data buffer,
while write access is to the transmit data buffer.
ISP Control Register
Bit:
7
6
5
4
3
2
1
0
SWRST/
REBOOT
-
LDAP
-
-
-
FBOOTSL FPROGEN
Mnemonic: CHPCON
Address: 9Fh
BIT
7
NAME
SWRST/
REBOOT
FUNCTION
Set this bit to launch a whole device reset that is same as asserting high to
RST pin, micro controller will be back to initial state and clear this bit
automatically. To read this bit, its alternate function to indicate the ISP
hardware reboot mode is invoking when reading it in high.
6
-
Reserved
5
LDAP
This bit is Read Only. High: device is executing the program in LD Flash
EPROM Low: device is executing the program in AP Flash EPROM.
4
-
Reserved
3
-
Reserved
2
-
Reserved
1
FBOOTSL Loader program residence selection. Set to high to route the device fetching
code from LD Flash EPROM.
FPROGEN In System Programming Mode Enable. Set this bit to launch the ISP mode.
Device will operate ISP procedures, such as Erase, Program and Read
operations, according to correlative SFRs settings. During ISP mode, device
achieves ISP operations by the way of IDLE state. In the other words, device is
not indeed in IDLE mode is set bit PCON.1 while ISP is enabled. Clear this bit
to disable ISP mode, device get back to normal operation including IDLE state.
0
Port 2
Bit:
7
6
5
4
3
2
1
0
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
Mnemonic: P2
Address: A0h
P2.7-0: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper
address bits for accesses to external memory.
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