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參數(shù)資料
| 型號(hào)： | W79E201A16PN |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | ROHS COMPLIANT, PLASTIC, LCC-44 |
| 文件頁數(shù)： | 49/87頁 |
| 文件大小： | 818K |
| 代理商： | W79E201A16PN |
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W79E201
Publication Release Date: December 16, 2004
- 49 -
Revision A2
any errant code is executed now, then the reset watchdog timer instructions will not be executed at
the required instants and watchdog reset will occur.
The watchdog time-out selection will result in different time-out values depending on the clock speed.
The reset, when enabled, it will occur 512 clocks after the time-out had occurred.
Table 9. Time-out values for the Watchdog timer
WD1
WD0
Watchdog
Interval
2
17
2
20
2
23
2
26
Number of
Clocks
Time
@ 1.8432 MHz
Time
@ 10 MHz
Time
@ 25 MHz
0
0
131072
71.11 mS
13.11 mS
5.24 mS
0
1
1048576
568.89 mS
104.86 mS
41.94 mS
1
0
8388608
4551.11 mS
838.86 mS
335.54 mS
1
1
67108864
36408.88 mS
6710.89 mS
2684.35 mS
The Watchdog timer will de disabled by a power-on/fail reset. The Watchdog timer reset does not
disable the watchdog timer, but will restart it. In general, software should restart the timer to put it into
a known state.
The control bits that support the Watchdog timer are discussed below.
Watchdog Control
BIT
7
NAME
-
FUNCTION
Reserved.
Power-on reset flag. Hardware will set this flag on a power up condition. This flag
can be read or written by software. A write by software is the only way to clear
this bit once it is set.
Reserved.
Reserved.
Watchdog Timer Interrupt Flag. If the watchdog interrupt is enabled, hardware will
set this bit to indicate that the watchdog interrupt has occurred. If the interrupt is
not enabled, then this bit indicates that the time-out period has elapsed. This bit
must be cleared by software.
Watchdog Timer Reset Flag. Hardware will set this bit when the watchdog timer
causes a reset. Software can read it but must clear it manually. A power-fail reset
will also clear the bit. This bit helps software in determining the cause of a reset. If
EWT = 0, the watchdog timer will have no affect on this bit.
Enable Watchdog timer Reset. Setting this bit will enable the Watchdog timer
Reset function.
Reset Watchdog Timer. This bit helps in putting the watchdog timer into a know
state. It also helps in resetting the watchdog timer before a time-out occurs.
Failing to set the EWT before time-out will cause an interrupt, if EWDI (EIE.4) is
set, and 512 clocks after that a watchdog timer reset will be generated if EWT is
set. This bit is self-clearing by hardware.
6
POR
5
4
-
-
3
WDIF
2
WTRF
1
EWT
0
RWT
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