
W79E804A/803A/802A
Publication Release Date: July 16, 2007
- 19 -
Revision A2
PORT 0
Bit:
7
6
5
4
3
2
1
0
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
Mnemonic: P0
P0.7-0: General purpose Input/Output port. Most instructions will read the port pins in case of a port
read access, however in case of read-modify-write instructions, the port latch is read. These alternate
functions are described below:
Address: 80h
BIT NAME
7
6
5
4
3
2
1
0
FUNCTION
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
Timer 1 pin or KB7 pin of keypad input.
CMP1 pin of analog comparator or KB6 pin of keypad input.
CMPREF pin of analog comparator or KB5 pin of keypad input.
CIN1A pin of analog comparator or KB4 pin of keypad input.
CIN1B pin of analog comparator or KB3 pin of keypad input.
BRAKE pin of PWM or CIN2A pin of analog comparator or KB2 pin of keypad input.
PWM0 pin or CIN2B pin of analog comparator or KB1 pin of keypad input.
PWM3 pin or CMP2 pin of analog comparator or KB0 pin of keypad input.
Note:
The initial value of the port is set by CONFIG1.PRHI bit. The default setting for CONFIG1.PRHI =1 which the alternative
function output is turned on upon reset. If CONFIG1.PRHI is set to 0, the user has to write a 1 to port SFR to turn on the
alternative function output.
STACK POINTER
Bit:
7
6
5
4
3
2
1
0
SP.7
SP.6
SP.5
SP.4
SP.3
SP.2
SP.1
SP.0
Mnemonic: SP
Address: 81h
BIT
NAME
FUNCTION
7-0
SP.[7:0]
The Stack Pointer stores the Scratch-pad RAM address where the stack begins. In
other words it always points to the top of the stack.
DATA POINTER LOW
Bit:
7
6
5
4
3
2
1
0
DPL.7
DPL.6
DPL.5
DPL.4
DPL.3
DPL.2
DPL.1
DPL.0
Mnemonic: DPL
Address: 82h
BIT
NAME
FUNCTION
7-0
DPL.[7:0] This is the low byte of the standard 8052 16-bit data pointer.
DATA POINTER HIGH
Bit:
7
6
5
4
3
2
1
0
DPH.7
DPH.6
DPH.5
DPH.4
DPH.3
DPH.2
DPH.1
DPH.0
Mnemonic: DPH
Address: 83h