
W79E804A/803A/802A
- 32 -
SLAVE ADDRESS MASK ENABLE 1
Bit:
7
6
5
4
3
2
1
0
I2DAT.7
I2DAT.6
I2DAT.5
I2DAT.4
I2DAT.3
I2DAT.2
I2DAT.1
I2DAT.0
Mnemonic: I2DAT
Address: BCh
BIT
NAME
FUNCTION
7-0
I2DAT.[7:0] The data register of I2C.
I2C STATUS REGISTER
Bit:
7
6
5
4
3
2
1
0
I2STATU
S.7
I2STATU
S.6
I2STATU
S.5
I2STATU
S.4
I2STATU
S.3
-
-
-
Mnemonic: I2STATUS
Address: BDh
BIT
NAME
FUNCTION
7-0
I2STATUS.[7:0]
The status register of I2C:
The three least significant bits are always 0. The five most significant bits
contain the status code. There are 23 possible status codes. When
I2STATUS contains F8H, no serial interrupt is requested. All other
I2STATUS values correspond to defined I2C states. When each of these
states is entered, a status interrupt is requested (SI = 1). A valid status
code is present in I2STATUS one machine cycle after SI is set by hardware
and is still present one machine cycle after SI has been reset by software.
In addition, states 00H stands for a Bus Error. A Bus Error occurs when a
START or STOP condition is present at an illegal position in the formation
frame. Example of illegal position are during the serial transfer of an
address byte, a data byte or an acknowledge bit.
I2C BAUD RATE CONTROL REGISTER
Bit:
7
6
5
4
3
2
1
0
I2CLK.7
I2CLK.6
I2CLK.5
I2CLK.4
I2CLK.3
I2CLK.2
I2CLK.1
I2CLK.0
Mnemonic: I2CLK
Address: BEh
BIT
NAME
FUNCTION
7-0
I2CLK.[7:0] The I2C clock rate bits.
I2C TIMER COUNTER REGISTER
Bit:
7
6
5
4
3
2
1
0
-
-
-
-
-
ENTI
DIV4
TIF
Mnemonic: I2TIMER
Address: BFh