
W79E804A/803A/802A
Publication Release Date: July 16, 2007
- 73 -
Revision A2
15.2 CLOCK CONTROL of Watchdog
WD1, WD0: WDCON.5, WDCON.4 - Watchdog Timer Mode select bits. These two bits select the
time-out interval for the watchdog timer. The reset time is 512 clocks longer than the interrupt time-out
value.
The default Watchdog time-out is 2
17
clocks, which is the shortest time-out period. The EWRST, WDIF
and WDCLR bits are protected by the Timed Access procedure. This prevents software from
accidentally enabling or disabling the watchdog timer. More importantly, it makes it highly improbable
that errant code can enable or disable the Watchdog Timer.
The security bit WDTE is located at bit 7 of CONFIG register. This bit is user to configure the clock
source of watchdog timer either it is from the internal RC or from the uC clock.
When WDTE bit is cleared and 500KHz clock is used to run the watchdog timer, there is a chance that
the watchdog timer would hang as the counter does not increment. This problem arises when the
watchdog is set to run, (WDCON.7, WDRUN), the WDCLR bit (WDCON.0) is set to clear the
watchdog timer and the next instruction is to set the PCON register for CPU to go into idle or power-
down state. The reason this happens because the setting/clearing of WDCLR bit and the watchdog
counter are running on different clock domains, CPU clock and internal RC clock respectively. When
WDCLR bit is set, to reset it, the counter must be non-zero. Since the counter is running off a much
slower clock, the counter may not have time to increment before the CPU clock halts as it entered the
idle/power-down mode. This results in the WDCLR bit is always set & the watchdog counter
remaining at zero. The solution to this problem is to monitor the WDCLR bit, ensuring that it’s cleared
before issue the instruction for the CPU to go into idle/power-down mode.