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參數資料
| 型號： | W79E804A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數： | 39/115頁 |
| 文件大小： | 1456K |
| 代理商： | W79E804A |
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W79E804A/803A/802A
Publication Release Date: July 16, 2007
- 39 -
Revision A2
BIT
NAME
FUNCTION
7
WDRUN
0: The Watchdog is stopped.
1: The Watchdog is running.
6
-
Reserved.
5
WD1
4
WD0
Watchdog Timer Time-out Select bits. These bits determine the time-out period
of the watchdog timer. The reset time-out period is 512 clocks longer than the
watchdog time-out.
WD1
WD0
Interrupt time-out
Reset time-out
2
17
+ 512
2
20
+ 512
2
23
+ 512
2
26
+ 512
0
0
2
17
2
20
2
23
2
26
0
1
1
0
1
1
3
WDIF
Watchdog Timer Interrupt Flag
0: If the interrupt is not enabled, then this bit indicates that the time-out period
has elapsed. This bit must be cleared by software.
1: If the watchdog interrupt is enabled, hardware will set this bit to indicate that
the watchdog interrupt has occurred.
2
WTRF
Watchdog Timer Reset Flag
1: Hardware will set this bit when the watchdog timer causes a reset. Software
can read it but must clear it manually. A power-fail reset will also clear the
bit. This bit helps software in determining the cause of a reset. If EWRST =
0, the watchdog timer will have no affect on this bit.
1
EWRST
0: Disable Watchdog Timer Reset.
1: Enable Watchdog Timer Reset.
0
WDCLR
Reset Watchdog Timer
This bit helps in putting the watchdog timer into a know state. It also helps in
resetting the watchdog timer before a time-out occurs. Failing to set the
EWRST before time-out will cause an interrupt, if EWDI (EIE.4) is set, and 512
clocks after that a watchdog timer reset will be generated if EWRST is set. This
bit is self-clearing by hardware.
The WDCON SFR is set to 0x000000B on a reset. WTRF (WDCON.2) is set to a 1 on a Watchdog
timer reset, but to a 0 on power on/down resets. WTRF (WDCON.2) is not altered by an
external
reset. EWRST (WDCON.1) is set to 0 on a Power-on reset, reset pin reset, and Watch Dog Timer
reset.
All the bits in this SFR have unrestricted read access. EWRST, WDIF and WDCLR require Timed
Access procedure to write. The remaining bits have unrestricted write accesses. Please refer TA
register description.
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