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參數資料
| 型號： | W79E804A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數： | 61/115頁 |
| 文件大小： | 1456K |
| 代理商： | W79E804A |
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W79E804A/803A/802A
Publication Release Date: July 16, 2007
- 61 -
Revision A2
If any of these conditions are not met, then the LCALL will not be generated. The polling cycle is
repeated every machine cycle, with the interrupts sampled in the same machine cycle. If an interrupt
flag is active in one cycle but not responded to, and is not active when the above conditions are met,
the denied interrupt will not be serviced. This means that active interrupts are not remembered; every
polling cycle is new.
The processor responds to a valid interrupt by executing an LCALL instruction to the appropriate
service routine. This may or may not clear the flag which caused the interrupt. In case of Timer
interrupts, the TF0 or TF1 flags are cleared by hardware whenever the processor vectors to the
appropriate timer service routine. In case of external interrupts,
INT0
and
INT1
, the flags are cleared
only if they are edge triggered. In case of Serial interrupts, the flags are not cleared by hardware. The
Watchdog timer interrupt flag WDIF has to be cleared by software. The hardware LCALL behaves
exactly like the software LCALL instruction. This instruction saves the Program Counter contents onto
the Stack, but does not save the Program Status Word PSW. The PC is reloaded with the vector
address of that interrupt which caused the LCALL. These address of vector for the different sources
are as follows:
VECTOR LOCATIONS FOR INTERRUPT SOURCES
SOURCE
VECTOR ADDRESS
SOURCE
VECTOR ADDRESS
External Interrupt 0
External Interrupt 1
Serial Port
I2C Interrupt
Comparator 2 Interrupt
Watchdog Timer
Comparator 1 Interrupt
PWM Brake Interrupt
0003h
0013h
0023h
0033h
0043h
0053h
0063h
0073h
Timer 0 Overflow
Timer 1 Overflow
Brownout Interrupt
KBI Interrupt
-
-
-
-
000Bh
001Bh
002Bh
003Bh
004Bh
005Bh
006Bh
007Bh
Table
12-1: Vector locations for interrupt sources
Execution continues from the vectored address till an RETI instruction is executed. On execution of
the RETI instruction the processor pops the Stack and loads the PC with the contents at the top of the
stack. The user must take care that the status of the stack is restored to what it was after the hardware
LCALL, if the execution is return to the interrupted program. The processor does not notice anything if
the stack contents are modified and will proceed with execution from the address put back into PC.
Note that a RET instruction would perform exactly the same process as a RETI instruction, but it
would not inform the Interrupt Controller that the interrupt service routine is completed, and would
leave the controller still thinking that the service routine is underway.
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