
W79E804A/803A/802A
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IP1 or IP1H and then executes a MUL or DIV instruction. From the time an interrupt source is
activated, the longest reaction time is 12 machine cycles. This includes 1 machine cycle to detect the
interrupt, 2 machine cycles to complete the IE, EIE, IP0, IP0H, IP1 or IP1H access, 5 machine cycles
to complete the MUL or DIV instruction and 4 machine cycles to complete the hardware LCALL to the
interrupt vector location.
Thus in a single-interrupt system the interrupt response time will always be more than 5 machine
cycles and not more than 12 machine cycles. The maximum latency of 12 machine cycles is 48 clock
cycles. Note that in the standard 8051 the maximum latency is 8 machine cycles which equals 96
machine cycles. This is a 50% reduction in terms of clock periods.
12.4 Interrupt Inputs
The W79E804 series have 12 interrupts source, and two individual interrupt inputs sources, one is for
IE0, IE1, BOF, KBF, WDT, CMF1 and CMF2, and other is IF0, IF1, RI+TI ,SI and BKF. Two interrupt
inputs are identical to those present on the standard 80C51 microcontroller as show in below figures.
If an external interrupt is enabled when the W79E804 series are put into Power Down or Idle mode,
the interrupt will cause the processor to wake up and resume operation.
IE0
EX0
IE1
EX1
BOF
EBO
KBF
EKB
WDT
EWDI
CM1
EC1
CM2
EC2
EA
Wakeup
(If in Power Down)
Interrupt
To CPU
Figure
12-1: Interrupt Sources that can wake up from Power Down Mode