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參數(shù)資料
| 型號： | W79E804A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 91/115頁 |
| 文件大小： | 1456K |
| 代理商： | W79E804A |
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W79E804A/803A/802A
Publication Release Date: July 16, 2007
- 91 -
Revision A2
23. PULSE-WIDTH-MODULATED (PWM) OUTPUTS
The W79E804 series have four Pulse Width Modulated (PWM) channels, and the PWM outputs are
PWM0 (P0.1), PWM1 (P1.6), PWM2 (P1.7) and PWM3 (P0.0). The initial PWM outputs level
correspondingly depend on the PRHI level set prior to the chip reset. When PRHI set to high, PWM
output will initialize to high after chip reset; if PRHI set to low, PWM output will be initialize to low after
chip reset.
The W79E804 series support 10-bits down counter with cpu clock as its input. The PWM counter
clock, has the same frequency as the clock source F
CPU
= F
OSC
. When the counter reaches underflow
it will automatic reloaded from counter register. The PWM frequency is given by: f
PWM
= F
CPU
/
(PWMP+1), where PWMP is 10-bits register of PWMPH.1, PWMPH.0 and PWMPL.7~PWMPL.0.
The counter register will be loaded with the PWMP register value when PWMRUN, load and CF are
equal to 1; the load bit will be automatically cleared to zero on the next clock cycle, and at the same
time the counter register value will be loaded to the 10 bits down counter. CF flag is 10-bits down
counter reaches underflow, the CF flag will be cleared by software.
The pulse width of each PWM output is determined by the Compare registers of PWM0L through
PWM3L and PWM0H through PWM3H. When PWM compare register is greater than 10-bits counter
register, the PWM output is low. Load bit has to be set to 1 for alteration of PWMn width. After the
new values are written to the PWMn registers, and if load bit is set to 1, the new PWMn values will be
loaded to the PWMn registers upon the next underflow. The PWM output high pulses width is given
by:
t
HI
= (PWMP – PWMn+1).
Notice, if compare register is set to 000H, the PWMn output will stay at
high, and if compare register is set to 3FFH, the PWMn output will stuck at low until there is a
change in the compare register.
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