
Preliminary W83196S-14
- 6 -
Set R/W to 1 when read back the data sequence is as follows:
Clock Address
A(6:0) & R/W
Ack
Byte 0
Ack
Ack
Byte2, 3, 4...
until Stop
Byte 1
7.3 Serial Control Registers
The Pin column lists the affected pin number and the @PowerUp column gives the state at true
power up. Registers are set to the values shown only on true power up. "Command Code" byte and
"Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data
(bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After
that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and
acknowledged.
Register 0 to Register 2 are referred to the Winbond SDRAM buffer(W83178S/179J) drivers.
7.3.1 Register 3: CPU Frequency Select Register (1 = Enable, 0 = Stopped)
BIT
7
6
5
4
3
@POWERUP
0
0
0
0
0
PIN
-
-
-
-
-
DESCRIPTION
Reserved
SSEL2 ( Frequency table selection by software via I
2
C)
SSEL1 ( Frequency table selection by software via I
2
C)
SSEL0 ( Frequency table selection by software via I
2
C)
0 = Selection by SEL100/66#
1 = Selection by software I
2
C - Bit 6:4 and Register 7 Bit0
Reserved
Bit1 Bit0 (See Function Table)
0 0 Normal
0 1 Test Mode
1 0
±
0.5% center type Spread Spectrum enabled
1 1 Tristate
2
0
00
-
-
1-0
(I) Default Frequency table selection by software via I
2
C (When Register 7 Bit 0 = 0 )
SSEL2
0
0
0
0
1
1
1
1
SSEL1
0
0
1
1
0
0
1
1
SSEL0
0
1
0
1
0
1
0
1
CPU, SDRAM (MHZ)
68.5
75
83.3
66.8
103
112
133.3
100
PCI (MHZ)
34.25
37.5
41.6
33.4
34.25
37.3
44.43
33.3
REF2X (MHZ)
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318