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參數資料
型號: W83196S-14
廠商: WINBOND ELECTRONICS CORP
元件分類: XO, clock
英文描述: 100 MHZ Clock For BX Chipset(2 Chip)(用于BX型芯片組的頻率為100MHZ的時鐘)
中文描述: 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
封裝: SOP-28
文件頁數: 9/15頁
文件大小: 217K
代理商: W83196S-14
Preliminary W83196S-14
Publication Release Date: March 1999
Revision A1
- 9 -
8.0 SPECIFICATIONS
8.1 Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device.
Precautions should be taken to avoid application of any voltage higher than the maximum rated
voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs
must always be tied to an appropriate logic voltage level (Ground or V
DD
).
PARAMETER
SYMBOL
V
DD
, V
IN
T
STG
T
B
T
A
RATING
-0.5V to +7.0V
-65
°
C to +150
°
C
-55
°
C to +125
°
C
0
°
C to +70
°
C
Voltage on Any Pin with Respect to GND
Storage Temperature
Ambient Temperature
Operating Temperature
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
8.2 AC Characteristics
V
DD
R = V
DD
Core = V
DD
P = V
DD
4 = 3.3V
±
5%, V
DD
A = V
DD
C = 2.5V
±
5% , T
A
= 0
°
C to +70
°
C
PARAMETER
Output Duty Cycle
CPU to PCI Offset
SYM.
MIN.
45
1
TYP.
50
MAX.
55
4
UNITS
%
nS
TEST CONDITIONS
Measured at 1.5V
15 pF Load Measured at
1.5V
15 pF Load Measured at
1.5V
t
OFF
Skew (CPU-CPU), (PCI-
PCI)
Cycle to Cycle Jitter
t
SKEW
250
ps
t
CCJ
200
ps
CPU
Absolute Jitter
Jitter Spectrum 20 dB
Bandwidth from Center
Output Rise (0.4V ~ 2.0V)
& Fall (2.0V ~0.4V) Time
t
JA
500
ps
BW
J
500
KHz
t
TLH
t
THL
V
over
0.4
1.6
nS
15 pF Load on CPU and
PCI outputs
Overshoot/Undershoot
Beyond Power Rails
Ring Back Exclusion
0.7
1.5
V
22
at source of 8 inch
PCB run to 15 pF load
V
RBE
0.7
2.1
V
Ring Back must not enter
this range.
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相關代理商/技術參數
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