
W83787IF
Publication Release Date:Sep 1995
- 35 -
Revision A1
3.0 IDE
The IDE interface is essentially the AT bus ported to the hard disk drive. The hard disk controller
resides on the IDE hard disk drive. So the IDE interface provides only chip select signals and AT bus
signals between the IDE hard disk drive and ISA slot. Table 3-1 shows the IDE registers and their ISA
addresses.
Table 3-1
I/O ADDRESS
REGISTERS
PRIMARY
1F0
1F1
1F2
1F3
1F4
1F5
1F6
1F7
3F6
3F7
SECONDARY
170
171
172
173
174
175
176
177
376
377
READ
WRITE
Data Register
Write-Precomp
Sector Count
Sector Number
Cylinder LOW
Cylinder HIGH
SDH Register
Command Register
Fixed Disk Control
Undefined
Data Register
Error Register
Sector Count
Sector Number
Cylinder LOW
Cylinder HIGH
SDH Register
Status Register
Alternate Status
Digital Input
3.1 IDE Decode Description
When the processor selects Ports 1F0-1F7 (or 170-177), the chip system enables
CS0
=
LOW;
otherwise, CS0
=
HIGH. When the processor selects Ports 3F6-3F7 (or 376-377), the chip system
enables
CS1
=
LOW; otherwise,
CS1 = HIGH.
4.0 UART PORT
4.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B)
The UARTs are used to convert parallel data into serial format on the transmit side and convert serial
data to parallel format on the receiver side. The serial format, in order of transmission and reception,
is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half
(five-bit format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65536 and
producing a 16x clock for driving the internal transmitter logic. Provisions are also included to use this
16x clock to drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore, the
UARTs also include complete modem control capability and a processor interrupt system that may be
software trailed to the computing time required to handle the communication link. The UARTs have a
FIFO mode to reduce the number of interrupts presented to the CPU. In each UART, there are 16-
byte FIFOs for both receive and transmit mode.