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參數資料
型號： W83787F
廠商： WINBOND ELECTRONICS CORP
英文描述： WINBOND I/O WITH SERIAL-INFRARED SUPPORT
中文描述： 華邦的I /串行O型紅外線支持
文件頁數： 38/123頁
文件大小： 1751K
代理商： W83787F
W83787IF
Publication Release Date:Sep 1995
- 38 -
Revision A1
TABLE 4 - 3 WORD LENGTH DEFINITION
DLS1
DLS0
DATA LENGTH
0
0
5 bits
0
1
6 bits
1
0
7 bits
1
1
8 bits
4.2.2 UART Status Register (USR) (Read/Write)
This 8-bit register provides information about the status of the data transfer during communication.
1
2
3
4
5
6
7
0
RBR Data ready (RDR)
Overrun error (OER)
Parity bit error (PBER)
No stop bit error (NSER)
Silent byte detected (SBD)
Transmitter Buffer Register empty (TBRE)
Transmitter Shift Register empty (TSRE)
RX FIFO Error Indication (RFEI)
Notes:
Bit 7: RFEI. In 16450 mode, this bit is always set to a logic 0. In 16550 mode, this bit is set to a logic
1 when there is at least one parity bit error, no stop bit error or silent byte detected in the FIFO.
In 16550 mode, this bit is cleared by reading from the USR if there are no remaining errors left
in the FIFO.
Bit 6: TSRE. In 16450 mode, when TBR and TSR are both empty, this bit will be set to a logical 1. In
16550 mode, if the transmit FIFO and TSR are both empty, it will be set to a logical 1. Other
than these two cases, this bit will be reset to a logical 0.
Bit 5: TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit will be
set to a logical 1. If ETREI of ICR is a logical 1, an interrupt will be generated to notify the CPU
to write the next data. In 16550 mode, this bit will be set to a logical 1 when the transmit FIFO
is
empty. It will be reset to a logical 0 when the CPU writes data into TBR or FIFO.
Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a
full
word time, including start bit, data bits, parity bit, and stop bits. In 16550 mode, it
indicates the
same condition for the data on top of the FIFO. When the CPU reads USR, it will
clear this bit
to a logical 0.
Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. In 16550
mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads
USR, it will clear this bit to a logical 0.
Bit 2: PBER. This bit is set to a logical 1 to indicate that the parity bit of received data is wrong. In
16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU
reads USR, it will clear this bit to a logical 0.
Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next
received data before they were read by the CPU. In 16550 mode, it indicates the same
condition instead of FIFO full. When the CPU reads USR, it will clear this bit to a logical 0.
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相關代理商/技術參數
參數描述
W83787IF 制造商:WINBOND 制造商全稱:Winbond 功能描述:WINBOND I/O WITH SERIAL-INFRARED SUPPORT
W83791D 制造商:WINBOND 制造商全稱:Winbond 功能描述:Winbond H/W Monitoring IC
W83791G 功能描述:IC MONITOR H/W 48-LQFP RoHS:是 類別:集成電路 (IC) >> PMIC - 熱管理 系列:- 標準包裝:1 系列:- 功能:溫度監控系統（傳感器） 傳感器類型:內部和外部 感應溫度:-40°C ~ 125°C，外部傳感器 精確度:±2.5°C 本地（最大值），±5°C 遠程（最大值） 拓撲:ADC，比較器，寄存器庫 輸出類型:2 線 SMBus? 輸出警報:無 輸出風扇:無 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-8 供應商設備封裝:SOT-23-8 包裝:Digi-Reel® 其它名稱:296-22675-6
W83791SD 制造商:WINBOND 制造商全稱:Winbond 功能描述:H/W MONITORING IC
W83791SG 制造商:WINBOND 制造商全稱:Winbond 功能描述:H/W MONITORING IC
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