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參數(shù)資料
| 型號(hào)： | W88113CF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 存儲(chǔ)控制器/管理單元 |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | IDE COMPATIBLE, CD ROM CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 45/102頁 |
| 文件大小： | 573K |
| 代理商： | W88113CF |
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W88113C
Publication Release Date: Mar. 1999
- 41 - Revision 0.61
MISC0 - Miscellaneous Control Register 0 - (write 2Eh)
Bit 7:
HIIEN - Host Interface Interrupt Enable
Setting this bit high enables the microprocessor interrupt of the host interface. Host interface
interrupt occurs at the following conditions:
SRST (Device Control Register) is written as 1 after 0 to either master or slave drive.
Execute Drive Diagnostics Command is written to either master or slave drive.
Any opcode is written to the ATAPI Command Register while the drive is selected except:
(1) command opcode is 08h, (2) command opcode is A0h and
APKTEN (18h.7)
is high.
IDE interface interrupt is cleared by the following:
Chip reset or host reset
Reading register 37h
Writing 1 to
CLRBSY (20h.4)
Bit 6:
Reserved
Bit 5:
DRVEb - Drive Selection Enable
Setting this bit low enables selection of the drive if bit DRV in ATAPI Drive Select Register
matches the setting of
MDRV (2Eh.4)
.
Bit 4:
MDRV - Master Drive
Setting this bit high sets the drive to be selected when bit DRV in the ATAPI Drive Select
Register is set to 0 (Master Drive).
Bit 3 : HIRQ - Host Interrupt Request
Set this bit high asserts interrupt at pin HIRQ if the drive is selected and nIEN is enabled in
the ATAPI Device Control Register. HIRQ is also automatically set by the following:
Automatic Packet Transfer sequence, enabled by
APKTEN (18h.7)
Automatic Status Completion sequence, enabled by
SCT (17h.w0)
or
ASCEN (18h.5)
HIRQ is automatically de-activated by the following:
Chip reset or host reset
Set bit SRST in the ATAPI Device Control Register high
Host issue ATA command while the drive is selected
Host read ATAPI Status Register while the drive is selected
Bit 2:
SHIEN - Shadow Command Interrupt Enable
Setting this bit high enables the microprocessor interrupt for the shadow command.
Pin
UINTb (36)
becomes low-active when
SHDC (2Fh.r5)
becomes high-active if this bit is
enabled.
Bit 1, 0: Reserved
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