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參數資料
| 型號： | W88113CF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | IDE COMPATIBLE, CD ROM CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數： | 94/102頁 |
| 文件大小： | 573K |
| 代理商： | W88113CF |
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W88113C
Publication Release Date: Mar. 1999
- 90 - Revision 0.61
5.4.10 Target Search
The target search logic is initialized by: (1) setting Search Limit, (2) setting Target and (3) setting
TARGEN (80h.w7)
high. After the decoding is triggered through
CTRL0 (0Ah,w),
the first sector
ready interrupt is generated when: i) the target sector is found, ii) header is larger than target or iii)
search limit is reached. If event ii) or iii) occurs, the microprocessor may read out
HEAD0-2 (04h-
06,r)
to determine the current distance from target. Setting
LTTIEN (80h.w2)
and
TNFEN (80h.w1)
high can generate the associated interrupt flag on
SRIb (01h.r5)
before the target is found.
decoder_on
Target(84h-86h) = T - 1
Tarctl(80h) = 8Fh
decoder_ini
set TSL(83h)
return
set BIA(09h/08h)
set DDB(29h/28h)
CTRL1(0Bh)
= F0h for mode 1
= F8h for mode 2
CTRL0(0Ah) = B7h
return
yes
SRIb(01h.r5)
yMonitor_Mode
HCEI(80h.0) or
STAERR(80h.6)
no
no
Cache
Management
yCache_Full
yes
decoder_stop
return
no
yes
yMonitor_Mode
CTRL0(0Ah) = 80h
no
TNFI(80h.1) or
LTTI(80h.2)
yes
yMonitor_Mode = 0
no
yMonitor_Mode = 1
decoder_on
return
yes
Mask(8Ch) = 80h
CTRLW(10h) = 50h
stop_decoder
CTRLW(10h) = 10h
return
CTRL0(0Ah) = 00h
5.4.11 Automatic Header Comparison
The automatic header comparison logic is enabled by setting
TARGEN (80h.w7)
and
HCEEN
(80h.w0)
high. After the first target is found, the value in
TARGET (84h-86h)
increases from
(T - 1)
to
T
. And the decoder is changed from disk-monitor mode to buffer-correction mode. Then
HEAD0-2
(04h-06h,r)
are compare with
TARGET (84h-86h)
and generate flag
HCEI (80h.r0)
at the end of EDC-
checking. Unless flag
STAERR (80h.r6)
or
HCEI (80h.r0)
is generated, the value in
TARGET (84h-
86h)
is automatically incremented by one and ready to be compared with next sector.
5.4.12 Status Collection
The status collection logic is enabled if any bit in the
Status-Mask-Register (8Ch-8Fh,w)
is set high.
At the end of EDC-checking, flag
STAERR (80h.r6)
becomes high if any status bit error that is
enabled by its associating mask bit occurs. The microprocessor can reduce the system overhead by
checking
STAERR (80h.r6)
rather than reading out
STAT (0Ch-0Fh,r)
.
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