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參數資料
| 型號： | W88113CF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | IDE COMPATIBLE, CD ROM CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數： | 60/102頁 |
| 文件大小： | 573K |
| 代理商： | W88113CF |
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W88113C
Publication Release Date: Mar. 1999
- 56 - Revision 0.61
TARSTA - Target Status Register - (read 80h)
This register is 0 after chip reset, host reset, firmware reset and decoder reset. Reading this register
deactivates
SRIb (01h.r5)
.
Bit 7: TARGED - Target Is Found
This bit is high after the target is found.
Bit 6: STAERR - Status Error Flag
This bit becomes high if any status bit error, enabled by its corresponding mask bit, occurs at
the end of EDC-checking. This flag is deactivated after reading register
TARSTA (80h,r)
.
Bit5: BIN0 - Block Indicator Is Not Zeror Flag
If
BIN0M (8Ch.w1)
is high, This bit becomes high if the block indicator in
HEAD3 (07h.r7-5)
is
not zero. This flag also activates
STAERR (80h.r5)
high.
Bit 4: DSFULI - Decoding Sector Full Interrupt Flag
If
DSCEN (80h.6)
is enabled, this flag becomes high if
DSCL (81h,r)
is equal to
DSTL (81h,w)
at the end of EDC-checking.
Bit 3: LASTBK - Last Decoded Block
If
BLIMEN (9Ah.5)
is high, this bit is set when the last pre-buffered block is decoded.
Firmware should disable decoder when detect this flag. The DSP buffering stop when buffer-
cache full.
Bit 2: LTTI - Larger Than Target Interrupt Flag
If
LTTEN (80h.w2)
and
TARGEN (80h.w7)
are high, this flag becomes high if the header
larger than target when
HEAD0-2 (04h-06h)
are available. This flag is deactivated after
reading register
TARSTA (80h,r).
Bit 1: TNFI - Target Not Founded Interrupt Flag
This bit becomes high if the headers in
HEAD0-2 (04h-06h)
never match the target after
N
successive comparisons. Where
N
is the search limit number specified by
TSL (83h,w
). If
TNFEN (80h.w1)
is high,
SRIb (01h.r5)
activates when this bit becomes high. If
ASTOPb
(80h.w3)
is low, this event also clears
DECEN (0AH.w7)
and stop the decoder automatically.
This flag is deactivated after reading register
TARSTA (80h,r)
. The microprocessor could
read out the header after event occurs to determine the distance from target.
Bit 0: HCEI - Header Compare Error Interrupt Flag
After target is founded, the number in
TARGET (84h-86h)
will automatically increment after
HEAD0-2 (04h-06h)
are available. If the headers of following sector do not match the target,
this bit becomes high and activates
SRIb (01h.r5)
if
HCEEN (80h.w0)
is enabled. It also
clears
DECEN (0AH.w7)
and stop the decoder automatically if
ASTOPb (80h.w3)
is low. This
flag is deactivated after reading register
TARSTA (80h,r)
.
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