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參數(shù)資料
型號： W88113CF
廠商： WINBOND ELECTRONICS CORP
元件分類： 存儲控制器/管理單元
英文描述： ATAPI CD-ROM DECODER & CONTROLLER
中文描述： IDE COMPATIBLE, CD ROM CONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 82/102頁
文件大小： 573K
代理商： W88113CF
W88113C
Publication Release Date: Mar. 1999
- 78 - Revision 0.61
5.1.3 Linear Address v.s. Block-Offset Address
The microprocessor can write/read external RAM through register
RAWR/RAMRD (1Eh)
based on
linear address defined by
RACU/H/L (2Dh/1Dh/1Ch,w)
. But the operation of data transfer from
DRAM to host can base on block-offset address or linear address. The following equation defines the
relation between these two types of address.
linear address = (block number block size) + address offset
<Example 1> Data Transfer in Working Area
Conditions: 64 bytes of TOC data are stored starting from linear address 3EA00h at disc initialization and
TOC is requested by host (block size is A00h).
A) Sequence at disc initialization:
a) set RACL (1Ch) as 00h
b) set RACH (1Dh) as EAh
c) set RACU (2Dh) as 03h
d) wait UTBY (1Fh.7) low
e) write data to register RAMWR (1Eh)
f) goto step e) until all 64 bytes are written to DRAM
B1) Setting for
block-offset address
transfer:
- set TBH/L (25h/24h) as 0064h
- set TACH/L (05h/04h) as 0200h
- set TWCH/L (03h/02h) as 001Fh
B2) Setting for
linear address
transfer:
- set RACL (1Ch) as 00h
- set RACH (1Dh) as EAh
- set RACU (2Dh) as 03h
- set TWCH/L (03h/02h) as 801Fh
<Example 2> Data Transfer in User Area
Conditions:
Mode 1 data.
The block number read from register DDBH/L (29h/28h) is 1Fh.
Case 1: The 2048 bytes of user data are requested by host.
set TBH/L (25h/24h) as 001Fh
set TWCH/L (03h/02h) as 03FFh
set TACH/L (05h/04h) as 0000h
Case 2: The 288 bytes of EDC&ECC data are request by host.
set TBH/L (25h/24h) as 001Fh
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