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參數資料
| 型號： | W89C841F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3-IN - 1 10/100M FAST ETHERNET CONTROLLER |
| 中文描述： | 2 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128 |
| 封裝： | 14 X 20 X 2.75 MM, QFP-128 |
| 文件頁數： | 11/102頁 |
| 文件大小： | 1154K |
| 代理商： | W89C841F |
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W89C841F/D
Publication Release Date: October 18, 2001
- 11 -
Revision A3
PCI Interface, continued
SIGNAL NAME
PIN TYP.
PIN NO.
DESCRIPTION
C_BEB[3:0]
IO/TS
5, 17, 28, 39
Multiplexed Command and Byte Enables
These signals are driven by current bus master.
During address phase, they mean a bus command.
On the other phase, they present the byte enable of
the transaction.
PAR
IO/TS
27
Parity Signal
This PAR represents the even parity across
AD[31:0] and C_BEB[3:0]. It has the same timing as
AD[31:0] but is delayed by one clock.
FRAMEB
IO/STS
18
PCI Cycle Frame
The current bus master asserts FRAMEB to
indicate the beginning and duration of a bus access.
This signal keeps asserted while the current
transaction is ongoing and keeps deasserted to
indicate that the next data phase is the final data
phase.
IRDYB
IO/STS
19
Initiator Ready
The IRDYB is asserted by the current initiator to
indicate the ability to complete the data transfer at
the current data phase. The initiator asserts IRDYB
to indicate the valid write data, or to indicate it is
ready to accept the read data.
More than or exactly
one wait state will be inserted if IRDYB is
deasserted during the current transaction. Data is
transferred at the clock rising edge
when both
IRDYB and TRDYB are asserted at the same time.
TRDYB
IO/STS
22
Target Ready
Asserted by the current target to indicate ability to
complete data transfer at the current data phase.
When W89C841F is operating at the bus slave
mode, it asserts TRDYB to indicate that the valid
read data presents on the bus or to indicate it is
ready to accept data. Wait states will be inserted if
TRDYB is deasserted. Data is transferred at the
rising edge of the PCI clock when IRDYB and
TRDYB are both asserted at the same time.
STOPB
IO/STS
24
PCI Stop
Asserted by the current target to request PCI bus
master to stop the current transaction.
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PDF描述 |
|---|---|
| W89C880F | 100Base-Tx/T4 Multiport Repeater Controller(100Base-Tx/T4多端口中繼器控制器) |
| W89C92 | PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER |
| W89C926 | PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER |
| W89C926F | 10M PCMCIA Ethernet Network Interface Controller |
| W89C940 | ELANC-PCI (TWISTED-PAIR ETHER-LAN CONTROLLER WITH PCI INTERFACE) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W89C841F/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3-IN-1 100BASE-TX/FX & 10BASE-T Ethernet Controller |
| W89C880F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Hub Controller |
| W89C92 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER |
| W89C926 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER |
| W89C926F | 制造商:WINBOND 制造商全稱:Winbond 功能描述:10M PCMCIA Ethernet Network Interface Controller |
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