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參數資料
| 型號： | W921F840 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 4-Bit Microcontroller(4位的微控制器) |
| 中文描述： | 4位微控制器（第4位的微控制器） |
| 文件頁數： | 22/68頁 |
| 文件大小： | 451K |
| 代理商： | W921F840 |
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W921F840
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6.6 Serial Port
The W921F840 has a clock-synchronous serial interface which transmits and receives 8-bit data as
default. User can program the P6IO register to select port P6 as the serial port. The serial
transmitter/receiver function can be operated with multi-nibble function and the LSB of every nibble is
transmitted/received first.
The serial transmitted/received data are come from or are stored into the serial buffer registers
(address 050H to 14EH) and how many nibbles will be transmitted/received is decided by the serial
MSB nibble register (SRMNR, address = 00AH) and serial LSB nibble register (SRLNR, address =
009H).
SRMNR register: (address = 00AH, default data = 0H)
b3
b2
b1
b0
SRLNR register: (address = 009H, default data = 2H)
b3
b2
b1
b0
The default data in SRMNR and SRLNR are 0 and 2, that means the default serial interface is used to
transmit/receive 8-bit data serially. As soon as the above two register are programmed and the
instructions such as SOP or SIP are executed, the serial transmitter/receiver multi-nibble function will
be performed. The transmitted/received number will be auto increased by one when each nibble is
transmitted/received until the number is equal to SRLNR, SRMNR registers. Even if the HOLD
instruction is executed, the SOP or SIP function will keep to execute until complete the
transmitter/receiver function. But execute the STOP instruction will stop all serial transmitter/receiver
function.
The transceiver data will be latched on the rising or falling edge of the clock is determined by the
serial clock inverter control register (SRINV, address = 00CH). Before SOP or SIP instruction is
executed the SRINV register must be set to the exact value. Once the bit3 and bit2 of SRINV register
are both cleared to zero, the serial transceiver function will be reset to initial status immediately.
SRINV register: (address = 00CH, default data = 0H)
b3
b2
b1
b0
0: Serial data latch at SCLK1/SCLK2 rising edge
(normal high)
1: Serial data latch at SCLK1/SCLK2 falling edge
(normal low)
1: SCLK1 and SDATA1 enable
1: SCLK2 and SDATA2 enable
0: SCLK1and SCLK2 pins work as the internal
clock output pin
1: SCLK1and SCLK2 pins work as the external
clock input pin
0: SCLK2 and SDATA2 disable (H-Z)
0: SCLK1 and SDATA1 disable (H-Z)
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