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參數資料
型號: W921F840
廠商: WINBOND ELECTRONICS CORP
英文描述: 4-Bit Microcontroller(4位的微控制器)
中文描述: 4位微控制器(第4位的微控制器)
文件頁數: 24/68頁
文件大小: 451K
代理商: W921F840
W921F840
- 24 -
Normally the SCLK1 or SCLK2 pin will keep in high state and the serial data will be latched at the
rising edge of the SCLK1 or SCLK2 signal, but the serial clock inverter control register (SRINV) will
invert the above function. In this case SCLK1 or SCLK2 pin will keep in low state and the serial data
will be latched at the falling edge of the SCLK1 or SCLK2 signal.
The transmitting serial clock can come from SCLK1 or SCLK2, depending on which one is enable. If
the serial function is disable, it will cause the relative pins to be high impendance and it will not affect
the contents of serial buffer registers (start at address 050H).
6.7 DTMF Generator
There is one channel of the dual tone multi-frequency (DTMF) generator in this chip. The correct
DTMF output frequency is decided by the OSCCTR register as shown below:
OSCCTR register: (address = 013H, default data = 0H)
b3
b2
b1
b0
Reserved
b2
b1
b0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Osc. Selection
400 KHz
800 KHz
2 MHz
4 MHz
Reserved
3.58MHz
There are four bits in the DTMF register; the functions are described in the following table:
DTMF register: (address = 014H, default data = 0H)
b3
b2
b1
b0
b3 b2 b1 b0
Function Description
X X 0 0
X X 0 1
X X 1 0
X X 1 1
0 0 X X
0 1 X X
1 0 X X
1 1 X X
Column 1 ( 1209 Hz ) output
Column 2 ( 1336 Hz ) output
Column 3 ( 1477 Hz ) output
Column 4 ( 1633 Hz ) output
Row 1 ( 697 Hz ) output
Row 2 ( 770 Hz ) output
Row 3 ( 852 Hz ) output
Row 4 ( 941 Hz ) output
Note: X
don't care
The output frequency of the row and column will be controlled by the row/column frequency control
register (RCCTL).
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