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參數資料
| 型號： | W9321 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | ADPCM Codec(ADPCM編解碼器) |
| 中文描述： | MU-LAW, ADPCM CODEC, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數： | 15/35頁 |
| 文件大小： | 457K |
| 代理商： | W9321 |
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Preliminary W9321
Publication Release Date: May 1999
- 15 -
Revision A1
8. CONTROL AND STATUS REGISTERS
8.1. Introduction
There are 16 available byte setup and status registers for the SSP port. The functional description
and read/write status of each bit are illustrated in the sections that follow. The read or write status
described in Table 8-1 is indicated by the symbol r, w, ro.
SYMBOL
r/w
TYPE
Read/Write
MEANING
Data may be read from the SSP port or written into the SSP
port by micro-processor
Data may only be read from the SSP port. Writing to this port
has no effect.
Read Only/Write Only Data may be read or written by an external micro-processor
and internal chip simultaneously. The value is written into the
bit and read back by the external micro-controller
ro
Read Only
ro/wo
Table 8-1 Read/Write Status Description in SSP Byte Register
8.2.
Byte Register Description
There are 16 byte registers for controlling and monitoring the status of the chip. These registers are
labeled BR0 to BR15. The descriptions are as follows. Note that "setting" is corresponding to logic "1”
and "clearing" is corresponding to logic "0".
.
8.2.1. Byte Register 0 (BR0)
This is a control register. All bits are cleared when the PDI/RESET pin is set to logic zero.
B7
B6
B5
B4
B3
B2
B1
B0
BR0
Ext 1024
KHz
Clock
r/w
Mu/A Law
Select
r/w
Analog
Loopback
r/w
Function
Mode
Select[1]
r/w
Function
Mode
Select[0]
r/w
Charge
Pump
Disable
r/w
Analog
Power
Down
r/w
Digital
Power
Down
r/w
External 1024 KHz Clock (b7):
This bit controls a mux. When this bit is cleared, the mux selects the 1024 KHz clock from the internal
clock generator. When this bit is set, the BCLKR pin is used to provide an external 1024 KHz clock
and the internal BCLKR is connected to BCLKT; the BR0[b1] must be set to "1" for reset codec.
Mu/A Law (b6):
When this bit is set to logic zero, the device selects Mu-Law companding of the Log-PCM. Setting this
bit selects the A-Law companding of the Log-PCM.
Analog Loopback (b5):
Setting this bit causes an analog loopback from the receive path to the transmit path. Internally the
RO output in the receive path is routed to the transmit gain control in the transmit path; the op-amp
TG is bypassed.
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