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參數(shù)資料
| 型號： | W9321 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | ADPCM Codec(ADPCM編解碼器) |
| 中文描述： | MU-LAW, ADPCM CODEC, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 9/35頁 |
| 文件大小： | 457K |
| 代理商： | W9321 |
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Preliminary W9321
Publication Release Date: May 1999
- 9 -
Revision A1
7.1.2. Power Supply for All Digital Signals Processing
All digital circuits are supplied by the V
DSP
pin from a 3-volt regulator circuit. This reduces the chip
power consumption. Whatever the value on the power supply pin V
EXT
, range from 2.7 to 5 volts, the
digital circuits will always be powered by a 3 volt voltage supply. Note that the V
DSP
pin should be
decoupled to Vss with a 0.1
μ
F capacitor and that this pin cannot be used for powering external loads.
7.1.3. Reference Voltage Control System
All analog reference voltages such as power amplifier RO, AXO, PO is 2.5 volt or V
EXT
/2 determined
by BR2(b7).
7.2.
Codec-Filter
This device has a built in linear 14-bit PCM codec-filter using
Σ
technology. There are two paths in
the block, a transmit path and a receive path.
7.2.1. Transmit Path in
An analog signal input, from a microphone interface, is passed to three terminal operational
amplifiers (TI+, TI-, TG) driving a typical 2 K
load externally to amplify the input analog signal. The
analog signal can then be set to have further transmission gain from 0 to +7 dB, in 1 dB steps by the
transmit gain control block. The gain is programmed through the SSP port in BR1(b2:b0). The
Σ
modulator block oversamples the analog signal at 1.024 MHz with one bit resolution. The next anti-
aliasing decimation filter reduces the sampling frequency from 1.024 MHz (1 bit) to 32 KHz (15 bit).
Digital biquad filters perform the decimation from 32K to 8 KHz and CCITT low-pass filtering at 3400
Hz. The digital HPF block performs the high-pass filtering at 300 Hz. In the final step, the 14 bit A/D
conversed data is sent by the transmit path to the DSP engine for further signal processing (e.g. by
the ADPCM encoder).
Codec-Filter
7.2.2. Receive Path in
A 14-bit linear digital signal from the Rx Attenuation control block in the DSP engine is first passed to
the digital anti-aliasing interpolation filter block. The interpolation block performs the reverse
operation of the decimation filter (described above in the transmit path) and the sampling rate will be
increased from 8 KHz (14 bits) to 1.024 MHz (14 bits). The digital
Σ
demodulator will then reduce
the 14-bit samples (1.024 MHz) to 1 bit (1.024 MHz). The digital output signal will be passed to a
3400 Hz switched capacitor low-pass filter with sin(x)/x correction and an analog smoothing filter to
reduce the spectral components of the switched capacitor filter. Finally, the analog output signal is
sent to the power amplifier, RO, which is capable of driving a 2 K
load connected to to the VAG pin,
and high current analog output driver AXO simultaneously with a 300
differential load.
Note the device provides another power amplifier, PO, connected in a push-pull configuration. The
AXO and PO have different circuit configurations for different applications. The AXO is for handset
ringer applications, but the PO driver can accommodate large gain ranges by adjusting two external
resistors for applications such as driving a telephone line or a handset receiver.
Codec-Filter
7.3. DSP Engine
This block is the kernel of the ADPCM transcoder and tone generator. There are two paths in this
block, a transmit path and a receive path.
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