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參數(shù)資料
| 型號(hào)： | W93902 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 尋呼電路 |
| 英文描述： | POCSAG Decoder For Pagers(尋呼機(jī)的POCSAG 解碼器) |
| 中文描述： | TELECOM, PAGING DECODER, PDSO24 |
| 封裝： | SSOP-24 |
| 文件頁數(shù)： | 14/22頁 |
| 文件大小： | 244K |
| 代理商： | W93902 |
W93902
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Note: When ERTR = 0, in the 4-bit package ER0 = 0, ER1 = 1, ER2 = 1, ER3 = Error flag.
*Generally, ER0 represents the parity error and ER1 represents the error condition before correction. ER2 represents the
burst error correction result and ER3 represents the random error correction result.
Data Transfer Timing
While the chip detects the proper address in the lock mode, the chip will send the message to the uC
from RXDATA pin as shown in figure 5. The detailed timing is depicted below.
RXDATA
Address word
First message word
A0
A1
A2
A3
A4
A5
A6
A7
RXCLK
(416 S to 26 S for 1200 bps)
(7.5 mS to 3.3 mS)
T
RXC1
T
RXC2
RXDATA
M0 M1 M2 M3 M4 M5
RXCLK
M6 M7
]
6.7 mS to 630 S)
Message word N-1
Message word N
Message word N+1
T
RXC3
RXDATA
T0
T1
T2
RXCLK
T3
T4
T5
T6
T7
Last message word
Termination word
Figure 8
Note: The timing of TRXC1, TRXC2, and TRXC3 depends on the setting of Ratel and Rate0.
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