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參數(shù)資料
| 型號： | W93902 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 尋呼電路 |
| 英文描述： | POCSAG Decoder For Pagers(尋呼機的POCSAG 解碼器) |
| 中文描述： | TELECOM, PAGING DECODER, PDSO24 |
| 封裝： | SSOP-24 |
| 文件頁數(shù)： | 21/22頁 |
| 文件大小： | 244K |
| 代理商： | W93902 |
W93902
Publication Release Date: October 1997
- 21 -
Revision A3
FOUT2 output control is similar, but the output stage is slightly different. When EFOUT2 is high, the
FOUT2 output clock is selected by the SF20 and SF21 bits, as shown in Table 28. When EFOUT2 is
low, FOUT2 provides a high-level dc output. Its output stage is a complementary CMOS output. It is
not necessary to connect a pull-up resistor.
The W93902 also supports a 32768 Hz real-time clock reference output, which is active after the
Txclk Wait Mode. When this clock output is not needed, the EFOUT1 bit should be set to 1.
FOUT1 and FOUT2 also provide a complementary clock output of 64 Hz, 16 Hz, or 1/60 Hz for use
as a reference timer.
Option EXTADD is used for proprietary algorithm. For normal operation, EXTADD should be set to 0.
DC CHARACTERISTICS
SYM.
PARAMETER
CONDITIONS
MIN.
TYP MAX. UNIT
Supply
V
DD
Supply voltage
2.5
3.0
5.0
V
I
SS
Supply current
V
DD
= 3 osc = 32 KHz
20
40
μ
A
μ
A
V
DD
= 3 osc = 76.8 KHz
25
45
Input
V
IH
High-level input voltage
NRZIN, TXCLK, TXDATA, ON,
XRESET, EFOUT2, AI, FBUZ1, FBUZ2
0.8
V
DD
V
IL
Low-level input voltage
NRZIN, TXCLK, TXDATA, ON,
XRESET, EFOUT2, AI, FBUZ1, FBUZ2
0.2
V
DD
I
IL
Low-level input current
XRESET, FBUZ1, FBUZ2
V
DD
= 3V,
V
IN
= 0V
10.0
μ
A
I
IH
High-level input current.
AI, EFOUT2
V
DD
= 3V,
V
IN
= 3V
10.0
μ
A
I
OL
Low-level output current
BS1, BS2, BS3, ADDDT, RXDATA,
RXCLK, SYNVZL, FOUT1, FOUT2
V
DD
= 2.7V,
V
OUT
= 1.35V
7.34
mA
I
OL
Low-level sink current.
FALM
V
DD
= 2.7V,
V
OUT
= 1.35V
14.68
mA
I
OH
High-level output current
BS1, BS2, BS3, ADDDT
RXDATA, RXCLK
SYNVAL, FOUT1, FOUT2
V
DD
= 2.7V,
V
OUT
= 1.35V
3.52
mA
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