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參數資料
| 型號： | W93902 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 尋呼電路 |
| 英文描述： | POCSAG Decoder For Pagers(尋呼機的POCSAG 解碼器) |
| 中文描述： | TELECOM, PAGING DECODER, PDSO24 |
| 封裝： | SSOP-24 |
| 文件頁數： | 7/22頁 |
| 文件大小： | 244K |
| 代理商： | W93902 |
W93902
Publication Release Date: October 1997
- 7 -
Revision A3
Lock Mode
If a synchronization codeword is detected in sync catch mode or in idle mode, then the chip enters
lock mode. While in the lock mode the chip will check the addresses assigned in Txclk wait mode. If a
matching address codeword appears, an ADDDT low signal will be generated and the message will
be received. The message will then be sent from the RXDATA pin and the data strobe clock will be
generated from RXCLK pin. The format used to send data from the RXDATA pin depends on the
options Convl and Conv2.
The data consist of an output address word followed by the message words and then terminated by a
termination word. The format is depicted below.
While in the lock mode, if the synchronization word is lost for a period of time, predefined by the
option Outr1, Outr2, and Eoutr, the chip will return to sync catch mode.
ON
BS1
BS2
BS3
T
BS3
T
BS2
32 bits No address detected
512 bits
Continue to receive message
T
BS3
ADDDT
PINT = 0
ADDDT
Address detected
PINT = 1
Address detected
ADDDT
RXDATA
Address word
Message word
Termination word
RXCLK
(43 mS for 512 bps,18.3 mS for 1200 bps)
22 data bits
PINT = 0
Figure 5
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相關代理商/技術參數 |
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