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參數資料
| 型號： | W93902 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 尋呼電路 |
| 英文描述： | POCSAG Decoder For Pagers(尋呼機的POCSAG 解碼器) |
| 中文描述： | TELECOM, PAGING DECODER, PDSO24 |
| 封裝： | SSOP-24 |
| 文件頁數： | 5/22頁 |
| 文件大小： | 244K |
| 代理商： | W93902 |
W93902
Publication Release Date: October 1997
- 5 -
Revision A3
XRESET
Total 128 clocks
TXCLK
At least 2 mS
At least 2 mS
TXDATA
D0
D1
D2
D3
D4
D5
D123 D124 D125 D126 D127
Figure 1. Programming Timing
Off Mode
After the W93902 has received 128 TXCLKs it will enter sync catch mode, if the ON pin is high, or off
mode, if the ON pin is low. When the chip is in off mode, all output pins are inactive except for the
Fout pin. Thus in off mode the chip provides only a timer reference clock function.
The chip can be switched on or off at any time by setting the ON pin to high or low, respectively.
Sync Catch Mode
In sync catch mode, the W93902 uses special timing to detect the synchronization codeword. First,
when the ON pin goes from low to high, BS1 and BS3 remain high for up to four batches (4.5 sec for
512 bps and 1.92 sec for 1200 bps) to search for the preamble codeword or synchronization
codeword. The detailed timing is shown below.
XRESET
TXCLK
At least 2 mS
At least 2 mS
Total 128 clocks
ON
BS1
4 batches
BS3
BS2
Figure 2
Note: The BS1 is to control the RF power, the BS2 is to discharge, and the BS3 is used to control the PLL power.
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