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參數資料
| 型號： | W9960CF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 消費家電 |
| 英文描述： | A Single Chip Multiprotcol High Performance Video CODEC(單片多協議高性能視頻編解碼器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數： | 26/65頁 |
| 文件大小： | 368K |
| 代理商： | W9960CF |
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W9960CF
Winbond Confidential
26
June 1997
3.5 External Memory DMA Controller ( XDMA )
There are 8 channels in XDMA which is used for direct memory accessing between PCI bus and
internal engines. While XDMA has DMA request, PCI interface will enter PCI master mode to
issue master cycles in PCI bus. The DMA transfer type supports both Demand Mode and Block
Mode, each with Linear Addressing or Blocking Addressing. Channel #0 and #1 are used to
transfer the remote and local picture out to system memory or graphic display device directly.
Channel #2 and #3 are used to transfer audio bitstream to external DSP coprocessor. Channel
#4 and #5 are used for video bitstream encoding and decoding. Channel #6 is used for firmware
downloading. Channel #7 is for verifying half-pixel search window memory. Channel #7should
not be activated in normal operation. The programming sequence is like the following:
1.
Setting DMA start address : programming XMSA register ( External Memory Start
Address register) with 32-bit access. The address should be double-word (4 bytes)
aligned.
2.
Setting DMA transfer mode : each channel has its own transfer mode register. The
register is accessed by two steps: set index value into XDMA Index register and then
write the data value into Height/Width register to set the Mode register (such as
Linear/Block Addressing, Demand/Block Transfer, direction, and size index)
3.
Setting DMA transfer size : the transfer size is defined by EH and EW registers. For
Block Addressing Mode, the transfer size is (EW+1)x(EH+1)x4 bytes; for Linear
Addressing Mode, the size is generated by concatenating EH and EW registers, i.e. the
transfer size is ({EH[8:0], EW[10:2]}+1)x4 bytes. XDMA provides 8 sets of EH and EW
registers as indicated by each XDMA channel from the Mode register setting. The
programming method of EH and EW register is the same as in programming Mode
registers.
4.
Setting frame size : XDMA , in Block Addressing Mode, refers to frame size of external
memory to generate the block address. XDMA provides 8 sets of PH and PW registers
to define the frame size (PW+1)x(PH+1)x4.
5.
Setting XTC Mask register: XTC Mask register indicates XDMA assert TC interrupt or
not.
6.
Setting XSDMA or XDMSK register: Host and VRISC can program XSDMA register to
trigger software DMA operation. XDMSK register is for enabling hardware triggered
DMA operations. Hardware engines can issue DMA requests to XDMA to trigger DMA
when the corresponding bits in the XDMASK register are set.
7.
Read XDTS register: while DMA operation has been completed and XDMA issues a TC
interrupt to host or VRISC, the interrupt service routine has to read the XDTS register
(TC status of XDMA) to clear the TC flag, so that the XDMA can continue with the next
DMA operation.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W9961CF | 制造商:WINBOND 制造商全稱:Winbond 功能描述:H.263/H.261 Video Codec |
| W9966CF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| W9966TF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| W99681CF | 制造商:WINBOND 制造商全稱:Winbond 功能描述:JPEG USB Dual Mode Camera Chip |
| W99685 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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