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參數資料
| 型號： | W9960CF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 消費家電 |
| 英文描述： | A Single Chip Multiprotcol High Performance Video CODEC(單片多協議高性能視頻編解碼器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數： | 7/65頁 |
| 文件大小： | 368K |
| 代理商： | W9960CF |
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W9960CF
Winbond Confidential
7
June 1997
2. PIN DESCRIPTION
2.1 Pin Definition
Pin Name
Pin No.
Type
Function
PCI BUS (50 pins)
AD31-AD0
204-205,4-9,
16-23, 42-49,
57-60, 65-68
IO
Address and Data are multiplexed on the same PCI pins. The
address phase is the clock cycle in which FRAME# is
asserted. During data phase AD7-AD0 contain the least
significant byte (lsb) and AD31-AD24 contain the most
significant byte (msb)
C/BE3-C/BE0 14,28,37,56
IO
Bus Command and Byte Enables are multiplexed on the
same PCI pins. During the address phase of a transaction,
C/BE3#-C/BE0# define the bus command. During the data
phase C/BE3#-C/BE0# are used as Byte Enable
PAR
36
IO
Parity is even parity across AD31-AD0 and C/BE3#-C/BE0#
FRAME#
29
IO
FRAME# is asserted to indicate a bus transaction is beginning
TRDY#
31
IO
Target Ready indicates the ability of target agent to complete
the current data phase of the transaction
IRDY#
30
IO
Initiator Ready indicates the ability of bus master to complete
the current data phase of the transaction.
INTA#
199
O
Interrupt A is used to request an interrupt
STOP#
33
IO
Stop indicates the current target is requesting the master to
stop the current transaction.
DEVSEL#
32
IO
Device Select, indicates the driving device has decoded its
address as the target of the current access
IDSEL
15
I
Initialization Device Select is used as chip select during
configuration read and write transactions.
PERR#
34
IO
Parity Error is for the reporting of data parity errors
SERR#
35
O
System Error is for reporting address parity errors, or any
other system error where the result will be catastrophic.
REQ#
203
O
Request indicates to the arbiter that W9960 desires use of the
bus
GNT#
202
I
Grant indicates that W9960 access to the bus has been
granted
CLK
201
I
PCI Clock
RST#
200
I
PCI Reset
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