
W9960CF
Winbond Confidential
30
June 1997
3.7 INTERRUPT/TRIGGER Controller
This controller provides 10 different Interrupts to VRISC and 5 triggering signals for VRISC to
trigger engines.
Trigger #0 is used for Video Capture triggering. Trigger #1 is used to start ME motion estimation
search. Trigger #2 is used to start FILTER block operation. Trigger #3 is used to trigger IDCT to
start decoding inverse discrete cosine transform operation. Trigger #4 is used to trigger DCT to
start encoding forward discrete cosine transform.
Interrupt #5 is XDMA Terminal Count Interrupt. Interrupt #6 is the interrupt coming from ISA-like
external interface. Interrupt #7 indicates the VLE FIFO full while T-coeff. encoding. Interrupt #8
and #9 are TIMER TR (Temporal Reference) Interrupts for decoding and encoding. Interrupt #10
and #11 are the TIMER time out interrupts. Interrupt #12 is used for host to interrupt VRISC.
Interrupt #13 indicates VLD operation is completed after VLD command register is triggered.
Interrupt #14 indicates the PIO BCH code is not aligned with frame. Interrupt #15 indicates a
Run-Level Block Error in VLD decoding.
All interrupts can be enabled or disabled as specified by the mask bits of the IMSK register. It will
response which channel is active on ISR register and generate an INT to VRISC. When VRISC
enters an interrupt service routine, it has to read out the IVEC register to have Interrupt
Controller assert INTA to clear interrupt status.
Signal
Type
INTG_IN
INTG_OUT
ENGINE
Description
0
TRIG
Capture_Trigger
VideoPre
Video Capture trigger
1
TRIG
MERDY
METG
ME
Trigger Motion Estimation
2
TRIG
FRDY
F_TRIGGER
FILTER
Trigger Filter
3
TRIG
TendINT
TriggerDEC
DCT/IDCT
Trigger IDCT
4
TRIG
RISCINT
TriggerENC
DCT/IDCT
Trigger DCT
5
INTR
int1
XDMA
XDMA TC Interrupt
6
INTR
extint
ISA-Like
ISA External Interrupt
7
INTR
VLE_INT
VLETCO
VLE FIFO Full Interrupt
8
INTR
DTR_INT
TIMER
Temp. Ref. Interrupt (Decoder)
9
INTR
ETR_INT
TIMER
Temp. Ref. Interrupt (Encoder)
10
INTR
TOUT0
TIMER
Timer 0 interrupt
11
INTR
TOUT1
TIMER
Timer 1 interrupt
12
INTR
PCI_INT
HOST
Host interrupt RISC
13
INTR
VLRDY_INT
TG_INTA
PIO
VLD is over
14
INTR UFRAME_INT UFRAME_INTA
PIO
Frame Un-lock Interrupt
15
INTR VLDREQ_INT VLDREQ_INTA
VLD
VLD Run Level Block Error