
W9960CF
Winbond Confidential
3
June 1997
1. INTRODUCTION.....................................................................................................5
1.1 O
VERVIEW
.................................................................................................................5
1.2 F
EATURES
..................................................................................................................6
2. PIN DESCRIPTION..................................................................................................7
2.1 P
IN
D
EFINITION
..........................................................................................................7
2.2 P
IN
O
UT
D
IAGRAM
.................................................................................................... 11
3. FUNCTIONAL DESCRIPTION ............................................................................ 12
3.1 W9960CF A
RCHITECTURE
....................................................................................... 12
3.2 PCI I
NTERFACE
........................................................................................................ 13
3.3 VRISC .................................................................................................................... 14
3.4 F
RAME
M
EMORY
DMA C
ONTROLLER
( FDMA )...................................................... 20
3.4.1 Bus Arbitration ................................................................................................. 21
3.4.2 FDMA Transfer Type........................................................................................ 21
3.4.3 FDMA Programming ........................................................................................ 22
3.4.4 FDMA Addressing Registers ............................................................................. 24
3.5 E
XTERNAL
M
EMORY
DMA C
ONTROLLER
( XDMA )................................................ 26
3.6 DRAM M
EMORY
I
NTERFACE
................................................................................... 28
3.7 INTERRUPT/TRIGGER C
ONTROLLER
................................................................... 30
3.8 X_INTERRUPT C
ONTROLLER
( XINTC )............................................................... 32
3.9 GPIO ( G
ENERAL
P
URPOSE
I
NPUT
/O
UPUT
) P
ORT
..................................................... 33
3.10 TIMER.................................................................................................................. 33
3.11 V
IDEO
P
RE
/P
OST
P
ROCESSING
E
NGINE
................................................................... 35
3.11.1 Video PreProcessor (VPRE)............................................................................ 35
3.11.2 Video PostProcessor (VPOST)......................................................................... 36
3.12 M
OTION
E
STIMATION
E
NGINE
................................................................................ 38
3.13 FILTER E
NGINE
.................................................................................................... 39
3.14 FIDCT/Q/IQ E
NGINE
............................................................................................. 42
3.15 P
ROGRAMMABLE
I
NPUT
/O
UTPUT
E
NGINE
............................................................... 44
3.16 V
ARIABLE
L
ENGTH
C
ODE
D
ECODER
....................................................................... 46
3.17 A
UDIO
C
OPROCESSOR
I
NTERFACE
.......................................................................... 47
3.18 V
ARIABLE
L
ENGTH
C
ODE
E
NCODING
(VLE) E
NGINE
.............................................. 48
3.19 ISA-
LIKE
I
NTERFACE
.............................................................................................. 49
4. W9960CF REGISTERS.......................................................................................... 51
4.1 PCI C
ONFIGURATION
R
EGISTERS
.............................................................................. 51
5. ELECTRICAL SPECIFICATIONS....................................................................... 57
5.1 A
BSOLUTE
M
AXIMUM
R
ATINGS
................................................................................ 57