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N8230DS1F
1.0 Product Description
The Bt8230 Segmentation and Reassembly Controller (SRC) incorporates a host
interface, ATM Adaptation Layer processing, and line interfaces in a single
device. This highly integrated Asynchronous Transfer Mode (ATM) device com-
bines several features such as a PCI bus interface, segmentation and reassembly
controllers, a local memory controller, a DMA coprocessor, and an automatic
scheduling algorithm. The Bt8230 supports all requirements contained in ATM
Forum User Network Interface Specification (UNI) 3.1 and the related American
National Standards Institute (ANSI) and International Telecommunications
Union (ITU) standards. The Bt8230’s architecture enables it to efficiently handle
high bandwidth throughput across the spectrum of two different ATM Adaptation
Layers (AALs) and two ATM service categories. Once initialized and given a seg-
mentation or reassembly task, the Bt8230 operates autonomously. This SRC com-
bines a Peripheral Component Interconnect (PCI) bus interface, segmentation and
reassembly controllers, a local memory controller, a Direct Memory Access
(DMA) coprocessor, and a proprietary scheduling algorithm that enables each
segmentation channel to achieve an independent bit rate of up to 200 Mbps per
channel for simplex connections.
Today's terminal adapters, routers/hubs, and other Wide Area Network (WAN)
applications require the features offered by the Bt8230. The device supports thou-
sands of connections simultaneously with robust Operation and Maintenance
(OAM), signaling, and Interim Local Management Interface (ILMI) features.
Other key features include support for random Virtual Path Identifier/ Virtual
Channel Identifier (VPI/VCI) assignment, interleaved AAL5 and AAL3/4 sup-
port, and termination of signaling and ILMI into local memory to maintain man-
agement connections independent of the host.
The Bt8230 incorporates an easy-to-use traffic priority management scheme
that allows each connection to be individually monitored. Both segmentation and
reassembly processes deal with host buffers as pipelines of information. Partial
packets may be added to the transmit stream or released as they are received for
additional processing by the host. The host buffer structures resemble those found
in common operating systems so the data can be processed by the host without the
need to physically copy the information to another memory location. A send
immediate mode supports low-latency connections. The Bt8230 transmit schedul-
ing algorithm supports the currently defined “leaky buckets.”
The optional local processor architecture provides the flexibility for system
designers and programmers to track the rapidly changing ATM standards. OAM,
ILMI, and signaling can all be ported to this processor to off-load the host system.
At the same time, a processor-less system is a cost-effective option with the
Bt8230 architecture. Therefore, this architecture is especially suited to ATM net-
work interfaces for file servers, routers/hubs, Digital Service Units (DSUs), and